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@@ -221,45 +221,41 @@ static int sch_gpio_probe(struct platform_device *pdev)
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gpio_ba = res->start;
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switch (id) {
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- case PCI_DEVICE_ID_INTEL_SCH_LPC:
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- sch_gpio_core.base = 0;
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- sch_gpio_core.ngpio = 10;
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-
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- sch_gpio_resume.base = 10;
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- sch_gpio_resume.ngpio = 4;
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-
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- /*
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- * GPIO[6:0] enabled by default
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- * GPIO7 is configured by the CMC as SLPIOVR
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- * Enable GPIO[9:8] core powered gpios explicitly
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- */
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- outb(0x3, gpio_ba + CGEN + 1);
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- /*
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- * SUS_GPIO[2:0] enabled by default
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- * Enable SUS_GPIO3 resume powered gpio explicitly
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- */
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- outb(0x8, gpio_ba + RGEN);
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- break;
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-
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- case PCI_DEVICE_ID_INTEL_ITC_LPC:
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- sch_gpio_core.base = 0;
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- sch_gpio_core.ngpio = 5;
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-
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- sch_gpio_resume.base = 5;
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- sch_gpio_resume.ngpio = 9;
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- break;
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-
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- case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
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- sch_gpio_core.base = 0;
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- sch_gpio_core.ngpio = 21;
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-
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- sch_gpio_resume.base = 21;
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- sch_gpio_resume.ngpio = 9;
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- break;
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-
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- default:
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- err = -ENODEV;
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- goto err_sch_gpio_core;
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+ case PCI_DEVICE_ID_INTEL_SCH_LPC:
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+ sch_gpio_core.base = 0;
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+ sch_gpio_core.ngpio = 10;
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+ sch_gpio_resume.base = 10;
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+ sch_gpio_resume.ngpio = 4;
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+ /*
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+ * GPIO[6:0] enabled by default
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+ * GPIO7 is configured by the CMC as SLPIOVR
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+ * Enable GPIO[9:8] core powered gpios explicitly
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+ */
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+ outb(0x3, gpio_ba + CGEN + 1);
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+ /*
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+ * SUS_GPIO[2:0] enabled by default
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+ * Enable SUS_GPIO3 resume powered gpio explicitly
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+ */
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+ outb(0x8, gpio_ba + RGEN);
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+ break;
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+
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+ case PCI_DEVICE_ID_INTEL_ITC_LPC:
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+ sch_gpio_core.base = 0;
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+ sch_gpio_core.ngpio = 5;
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+ sch_gpio_resume.base = 5;
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+ sch_gpio_resume.ngpio = 9;
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+ break;
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+
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+ case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
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+ sch_gpio_core.base = 0;
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+ sch_gpio_core.ngpio = 21;
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+ sch_gpio_resume.base = 21;
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+ sch_gpio_resume.ngpio = 9;
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+ break;
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+
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+ default:
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+ err = -ENODEV;
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+ goto err_sch_gpio_core;
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}
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sch_gpio_core.dev = &pdev->dev;
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