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@@ -1910,56 +1910,27 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
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(dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
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/*
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- * Program the relevant mask registers. If src/dst_port or src/dst_addr
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- * are zero, then assume a full mask for that field. Also assume that
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- * a VLAN of 0 is unspecified, so mask that out as well. L4type
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- * cannot be masked out in this implementation.
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+ * Program the relevant mask registers. L4type cannot be
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+ * masked out in this implementation.
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*
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* This also assumes IPv4 only. IPv6 masking isn't supported at this
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* point in time.
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*/
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- if (src_ipv4 == 0)
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- IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xffffffff);
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- else
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- IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask);
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-
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- if (dst_ipv4 == 0)
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- IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xffffffff);
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- else
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- IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask);
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+ IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask);
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+ IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask);
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switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
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case IXGBE_ATR_L4TYPE_TCP:
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- if (src_port == 0)
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- IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xffff);
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- else
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- IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
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- input_masks->src_port_mask);
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-
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- if (dst_port == 0)
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- IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
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- (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
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- (0xffff << 16)));
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- else
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- IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
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- (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
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- (input_masks->dst_port_mask << 16)));
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+ IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, input_masks->src_port_mask);
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+ IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
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+ (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
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+ (input_masks->dst_port_mask << 16)));
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break;
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case IXGBE_ATR_L4TYPE_UDP:
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- if (src_port == 0)
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- IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xffff);
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- else
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- IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
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- input_masks->src_port_mask);
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-
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- if (dst_port == 0)
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- IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
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- (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
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- (0xffff << 16)));
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- else
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- IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
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- (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
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- (input_masks->src_port_mask << 16)));
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+ IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, input_masks->src_port_mask);
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+ IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
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+ (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
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+ (input_masks->src_port_mask << 16)));
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break;
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default:
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/* this already would have failed above */
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@@ -1967,11 +1938,11 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
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}
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/* Program the last mask register, FDIRM */
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- if (input_masks->vlan_id_mask || !vlan_id)
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+ if (input_masks->vlan_id_mask)
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/* Mask both VLAN and VLANP - bits 0 and 1 */
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fdirm |= 0x3;
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- if (input_masks->data_mask || !flex_bytes)
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+ if (input_masks->data_mask)
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/* Flex bytes need masking, so mask the whole thing - bit 4 */
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fdirm |= 0x10;
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