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@@ -44,9 +44,7 @@
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#include <plat/mcspi.h>
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#define OMAP2_MCSPI_MAX_FREQ 48000000
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-
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-/* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
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-#define OMAP2_MCSPI_MAX_CTRL 4
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+#define SPI_AUTOSUSPEND_TIMEOUT 2000
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#define OMAP2_MCSPI_REVISION 0x00
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#define OMAP2_MCSPI_SYSSTATUS 0x14
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@@ -111,19 +109,25 @@ struct omap2_mcspi_dma {
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#define DMA_MIN_BYTES 160
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+/*
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+ * Used for context save and restore, structure members to be updated whenever
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+ * corresponding registers are modified.
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+ */
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+struct omap2_mcspi_regs {
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+ u32 modulctrl;
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+ u32 wakeupenable;
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+ struct list_head cs;
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+};
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+
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struct omap2_mcspi {
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- struct work_struct work;
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- /* lock protects queue and registers */
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- spinlock_t lock;
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- struct list_head msg_queue;
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struct spi_master *master;
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/* Virtual base address of the controller */
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void __iomem *base;
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unsigned long phys;
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/* SPI1 has 4 channels, while SPI2 has 2 */
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struct omap2_mcspi_dma *dma_channels;
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- struct device *dev;
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- struct workqueue_struct *wq;
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+ struct device *dev;
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+ struct omap2_mcspi_regs ctx;
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};
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struct omap2_mcspi_cs {
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@@ -135,17 +139,6 @@ struct omap2_mcspi_cs {
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u32 chconf0;
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};
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-/* used for context save and restore, structure members to be updated whenever
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- * corresponding registers are modified.
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- */
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-struct omap2_mcspi_regs {
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- u32 modulctrl;
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- u32 wakeupenable;
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- struct list_head cs;
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-};
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-
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-static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL];
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-
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#define MOD_REG_BIT(val, mask, set) do { \
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if (set) \
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val |= mask; \
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@@ -236,9 +229,12 @@ static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
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static void omap2_mcspi_set_master_mode(struct spi_master *master)
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{
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+ struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
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+ struct omap2_mcspi_regs *ctx = &mcspi->ctx;
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u32 l;
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- /* setup when switching from (reset default) slave mode
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+ /*
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+ * Setup when switching from (reset default) slave mode
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* to single-channel master mode
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*/
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l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
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@@ -247,29 +243,26 @@ static void omap2_mcspi_set_master_mode(struct spi_master *master)
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MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
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mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
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- omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
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+ ctx->modulctrl = l;
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}
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static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
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{
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- struct spi_master *spi_cntrl;
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- struct omap2_mcspi_cs *cs;
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- spi_cntrl = mcspi->master;
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+ struct spi_master *spi_cntrl = mcspi->master;
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+ struct omap2_mcspi_regs *ctx = &mcspi->ctx;
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+ struct omap2_mcspi_cs *cs;
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/* McSPI: context restore */
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- mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
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- omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
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-
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- mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
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- omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
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+ mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
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+ mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
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- list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs,
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- node)
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+ list_for_each_entry(cs, &ctx->cs, node)
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__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
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}
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static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
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{
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- pm_runtime_put_sync(mcspi->dev);
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+ pm_runtime_mark_last_busy(mcspi->dev);
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+ pm_runtime_put_autosuspend(mcspi->dev);
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}
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static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
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@@ -277,6 +270,23 @@ static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
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return pm_runtime_get_sync(mcspi->dev);
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}
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+static int omap2_prepare_transfer(struct spi_master *master)
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+{
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+ struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
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+
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+ pm_runtime_get_sync(mcspi->dev);
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+ return 0;
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+}
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+
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+static int omap2_unprepare_transfer(struct spi_master *master)
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+{
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+ struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
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+
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+ pm_runtime_mark_last_busy(mcspi->dev);
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+ pm_runtime_put_autosuspend(mcspi->dev);
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+ return 0;
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+}
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+
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static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
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{
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unsigned long timeout;
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@@ -777,7 +787,8 @@ static int omap2_mcspi_request_dma(struct spi_device *spi)
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static int omap2_mcspi_setup(struct spi_device *spi)
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{
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int ret;
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- struct omap2_mcspi *mcspi;
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+ struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
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+ struct omap2_mcspi_regs *ctx = &mcspi->ctx;
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struct omap2_mcspi_dma *mcspi_dma;
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struct omap2_mcspi_cs *cs = spi->controller_state;
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@@ -787,11 +798,10 @@ static int omap2_mcspi_setup(struct spi_device *spi)
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return -EINVAL;
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}
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- mcspi = spi_master_get_devdata(spi->master);
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mcspi_dma = &mcspi->dma_channels[spi->chip_select];
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if (!cs) {
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- cs = kzalloc(sizeof *cs, GFP_KERNEL);
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+ cs = devm_kzalloc(&spi->dev , sizeof *cs, GFP_KERNEL);
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if (!cs)
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return -ENOMEM;
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cs->base = mcspi->base + spi->chip_select * 0x14;
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@@ -799,8 +809,7 @@ static int omap2_mcspi_setup(struct spi_device *spi)
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cs->chconf0 = 0;
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spi->controller_state = cs;
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/* Link this to context save list */
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- list_add_tail(&cs->node,
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- &omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs);
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+ list_add_tail(&cs->node, &ctx->cs);
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}
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if (mcspi_dma->dma_rx_channel == -1
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@@ -833,7 +842,6 @@ static void omap2_mcspi_cleanup(struct spi_device *spi)
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cs = spi->controller_state;
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list_del(&cs->node);
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- kfree(spi->controller_state);
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}
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if (spi->chip_select < spi->master->num_chipselect) {
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@@ -850,144 +858,122 @@ static void omap2_mcspi_cleanup(struct spi_device *spi)
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}
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}
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-static void omap2_mcspi_work(struct work_struct *work)
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+static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
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{
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- struct omap2_mcspi *mcspi;
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-
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- mcspi = container_of(work, struct omap2_mcspi, work);
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-
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- if (omap2_mcspi_enable_clocks(mcspi) < 0)
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- return;
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-
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- spin_lock_irq(&mcspi->lock);
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/* We only enable one channel at a time -- the one whose message is
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- * at the head of the queue -- although this controller would gladly
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+ * -- although this controller would gladly
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* arbitrate among multiple channels. This corresponds to "single
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* channel" master mode. As a side effect, we need to manage the
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* chipselect with the FORCE bit ... CS != channel enable.
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*/
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- while (!list_empty(&mcspi->msg_queue)) {
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- struct spi_message *m;
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- struct spi_device *spi;
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- struct spi_transfer *t = NULL;
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- int cs_active = 0;
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- struct omap2_mcspi_cs *cs;
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- struct omap2_mcspi_device_config *cd;
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- int par_override = 0;
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- int status = 0;
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- u32 chconf;
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-
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- m = container_of(mcspi->msg_queue.next, struct spi_message,
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- queue);
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-
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- list_del_init(&m->queue);
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- spin_unlock_irq(&mcspi->lock);
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-
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- spi = m->spi;
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- cs = spi->controller_state;
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- cd = spi->controller_data;
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- omap2_mcspi_set_enable(spi, 1);
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- list_for_each_entry(t, &m->transfers, transfer_list) {
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- if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
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- status = -EINVAL;
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- break;
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- }
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- if (par_override || t->speed_hz || t->bits_per_word) {
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- par_override = 1;
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- status = omap2_mcspi_setup_transfer(spi, t);
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- if (status < 0)
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- break;
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- if (!t->speed_hz && !t->bits_per_word)
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- par_override = 0;
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- }
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+ struct spi_device *spi;
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+ struct spi_transfer *t = NULL;
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+ int cs_active = 0;
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+ struct omap2_mcspi_cs *cs;
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+ struct omap2_mcspi_device_config *cd;
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+ int par_override = 0;
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+ int status = 0;
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+ u32 chconf;
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- if (!cs_active) {
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- omap2_mcspi_force_cs(spi, 1);
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- cs_active = 1;
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- }
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+ spi = m->spi;
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+ cs = spi->controller_state;
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+ cd = spi->controller_data;
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- chconf = mcspi_cached_chconf0(spi);
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- chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
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- chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
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+ omap2_mcspi_set_enable(spi, 1);
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+ list_for_each_entry(t, &m->transfers, transfer_list) {
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+ if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
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+ status = -EINVAL;
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+ break;
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+ }
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+ if (par_override || t->speed_hz || t->bits_per_word) {
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+ par_override = 1;
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+ status = omap2_mcspi_setup_transfer(spi, t);
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+ if (status < 0)
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+ break;
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+ if (!t->speed_hz && !t->bits_per_word)
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+ par_override = 0;
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+ }
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- if (t->tx_buf == NULL)
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- chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
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- else if (t->rx_buf == NULL)
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- chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
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-
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- if (cd && cd->turbo_mode && t->tx_buf == NULL) {
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- /* Turbo mode is for more than one word */
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- if (t->len > ((cs->word_len + 7) >> 3))
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- chconf |= OMAP2_MCSPI_CHCONF_TURBO;
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- }
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+ if (!cs_active) {
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+ omap2_mcspi_force_cs(spi, 1);
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+ cs_active = 1;
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+ }
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- mcspi_write_chconf0(spi, chconf);
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+ chconf = mcspi_cached_chconf0(spi);
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+ chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
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+ chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
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- if (t->len) {
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- unsigned count;
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+ if (t->tx_buf == NULL)
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+ chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
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+ else if (t->rx_buf == NULL)
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+ chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
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- /* RX_ONLY mode needs dummy data in TX reg */
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- if (t->tx_buf == NULL)
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- __raw_writel(0, cs->base
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- + OMAP2_MCSPI_TX0);
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+ if (cd && cd->turbo_mode && t->tx_buf == NULL) {
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+ /* Turbo mode is for more than one word */
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+ if (t->len > ((cs->word_len + 7) >> 3))
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+ chconf |= OMAP2_MCSPI_CHCONF_TURBO;
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+ }
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- if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
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- count = omap2_mcspi_txrx_dma(spi, t);
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- else
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- count = omap2_mcspi_txrx_pio(spi, t);
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- m->actual_length += count;
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+ mcspi_write_chconf0(spi, chconf);
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- if (count != t->len) {
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- status = -EIO;
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- break;
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- }
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- }
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+ if (t->len) {
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+ unsigned count;
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- if (t->delay_usecs)
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- udelay(t->delay_usecs);
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+ /* RX_ONLY mode needs dummy data in TX reg */
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+ if (t->tx_buf == NULL)
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+ __raw_writel(0, cs->base
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+ + OMAP2_MCSPI_TX0);
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+
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+ if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
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+ count = omap2_mcspi_txrx_dma(spi, t);
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+ else
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+ count = omap2_mcspi_txrx_pio(spi, t);
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+ m->actual_length += count;
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- /* ignore the "leave it on after last xfer" hint */
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- if (t->cs_change) {
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- omap2_mcspi_force_cs(spi, 0);
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- cs_active = 0;
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+ if (count != t->len) {
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+ status = -EIO;
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+ break;
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}
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}
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- /* Restore defaults if they were overriden */
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- if (par_override) {
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- par_override = 0;
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- status = omap2_mcspi_setup_transfer(spi, NULL);
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- }
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+ if (t->delay_usecs)
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+ udelay(t->delay_usecs);
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- if (cs_active)
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+ /* ignore the "leave it on after last xfer" hint */
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+ if (t->cs_change) {
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omap2_mcspi_force_cs(spi, 0);
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+ cs_active = 0;
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+ }
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+ }
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+ /* Restore defaults if they were overriden */
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+ if (par_override) {
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+ par_override = 0;
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+ status = omap2_mcspi_setup_transfer(spi, NULL);
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+ }
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- omap2_mcspi_set_enable(spi, 0);
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-
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- m->status = status;
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- m->complete(m->context);
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+ if (cs_active)
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+ omap2_mcspi_force_cs(spi, 0);
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- spin_lock_irq(&mcspi->lock);
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- }
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+ omap2_mcspi_set_enable(spi, 0);
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- spin_unlock_irq(&mcspi->lock);
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+ m->status = status;
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- omap2_mcspi_disable_clocks(mcspi);
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}
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-static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
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+static int omap2_mcspi_transfer_one_message(struct spi_master *master,
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+ struct spi_message *m)
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{
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struct omap2_mcspi *mcspi;
|
|
|
- unsigned long flags;
|
|
|
struct spi_transfer *t;
|
|
|
|
|
|
+ mcspi = spi_master_get_devdata(master);
|
|
|
m->actual_length = 0;
|
|
|
m->status = 0;
|
|
|
|
|
|
/* reject invalid messages and transfers */
|
|
|
- if (list_empty(&m->transfers) || !m->complete)
|
|
|
+ if (list_empty(&m->transfers))
|
|
|
return -EINVAL;
|
|
|
list_for_each_entry(t, &m->transfers, transfer_list) {
|
|
|
const void *tx_buf = t->tx_buf;
|
|
@@ -999,7 +985,7 @@ static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
|
|
|
|| (t->bits_per_word &&
|
|
|
( t->bits_per_word < 4
|
|
|
|| t->bits_per_word > 32))) {
|
|
|
- dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
|
|
|
+ dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
|
|
|
t->speed_hz,
|
|
|
len,
|
|
|
tx_buf ? "tx" : "",
|
|
@@ -1008,7 +994,7 @@ static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
|
|
|
return -EINVAL;
|
|
|
}
|
|
|
if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
|
|
|
- dev_dbg(&spi->dev, "speed_hz %d below minimum %d Hz\n",
|
|
|
+ dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
|
|
|
t->speed_hz,
|
|
|
OMAP2_MCSPI_MAX_FREQ >> 15);
|
|
|
return -EINVAL;
|
|
@@ -1018,51 +1004,46 @@ static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
|
|
|
continue;
|
|
|
|
|
|
if (tx_buf != NULL) {
|
|
|
- t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
|
|
|
+ t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
|
|
|
len, DMA_TO_DEVICE);
|
|
|
- if (dma_mapping_error(&spi->dev, t->tx_dma)) {
|
|
|
- dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
|
|
|
+ if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
|
|
|
+ dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
|
|
|
'T', len);
|
|
|
return -EINVAL;
|
|
|
}
|
|
|
}
|
|
|
if (rx_buf != NULL) {
|
|
|
- t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
|
|
|
+ t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
|
|
|
DMA_FROM_DEVICE);
|
|
|
- if (dma_mapping_error(&spi->dev, t->rx_dma)) {
|
|
|
- dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
|
|
|
+ if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
|
|
|
+ dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
|
|
|
'R', len);
|
|
|
if (tx_buf != NULL)
|
|
|
- dma_unmap_single(&spi->dev, t->tx_dma,
|
|
|
+ dma_unmap_single(mcspi->dev, t->tx_dma,
|
|
|
len, DMA_TO_DEVICE);
|
|
|
return -EINVAL;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
- mcspi = spi_master_get_devdata(spi->master);
|
|
|
-
|
|
|
- spin_lock_irqsave(&mcspi->lock, flags);
|
|
|
- list_add_tail(&m->queue, &mcspi->msg_queue);
|
|
|
- queue_work(mcspi->wq, &mcspi->work);
|
|
|
- spin_unlock_irqrestore(&mcspi->lock, flags);
|
|
|
-
|
|
|
+ omap2_mcspi_work(mcspi, m);
|
|
|
+ spi_finalize_current_message(master);
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
|
|
|
{
|
|
|
struct spi_master *master = mcspi->master;
|
|
|
- u32 tmp;
|
|
|
- int ret = 0;
|
|
|
+ struct omap2_mcspi_regs *ctx = &mcspi->ctx;
|
|
|
+ int ret = 0;
|
|
|
|
|
|
ret = omap2_mcspi_enable_clocks(mcspi);
|
|
|
if (ret < 0)
|
|
|
return ret;
|
|
|
|
|
|
- tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
|
|
|
- mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
|
|
|
- omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp;
|
|
|
+ mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
|
|
|
+ OMAP2_MCSPI_WAKEUPENABLE_WKEN);
|
|
|
+ ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
|
|
|
|
|
|
omap2_mcspi_set_master_mode(master);
|
|
|
omap2_mcspi_disable_clocks(mcspi);
|
|
@@ -1102,14 +1083,13 @@ static const struct of_device_id omap_mcspi_of_match[] = {
|
|
|
};
|
|
|
MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
|
|
|
|
|
|
-static int __init omap2_mcspi_probe(struct platform_device *pdev)
|
|
|
+static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
|
|
|
{
|
|
|
struct spi_master *master;
|
|
|
struct omap2_mcspi_platform_config *pdata;
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
struct resource *r;
|
|
|
int status = 0, i;
|
|
|
- char wq_name[20];
|
|
|
u32 regs_offset = 0;
|
|
|
static int bus_num = 1;
|
|
|
struct device_node *node = pdev->dev.of_node;
|
|
@@ -1125,7 +1105,9 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
|
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
|
|
|
|
|
master->setup = omap2_mcspi_setup;
|
|
|
- master->transfer = omap2_mcspi_transfer;
|
|
|
+ master->prepare_transfer_hardware = omap2_prepare_transfer;
|
|
|
+ master->unprepare_transfer_hardware = omap2_unprepare_transfer;
|
|
|
+ master->transfer_one_message = omap2_mcspi_transfer_one_message;
|
|
|
master->cleanup = omap2_mcspi_cleanup;
|
|
|
master->dev.of_node = node;
|
|
|
|
|
@@ -1150,13 +1132,6 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
|
|
|
mcspi = spi_master_get_devdata(master);
|
|
|
mcspi->master = master;
|
|
|
|
|
|
- sprintf(wq_name, "omap2_mcspi/%d", master->bus_num);
|
|
|
- mcspi->wq = alloc_workqueue(wq_name, WQ_MEM_RECLAIM, 1);
|
|
|
- if (mcspi->wq == NULL) {
|
|
|
- status = -ENOMEM;
|
|
|
- goto free_master;
|
|
|
- }
|
|
|
-
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
if (r == NULL) {
|
|
|
status = -ENODEV;
|
|
@@ -1166,32 +1141,24 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
|
|
|
r->start += regs_offset;
|
|
|
r->end += regs_offset;
|
|
|
mcspi->phys = r->start;
|
|
|
- if (!request_mem_region(r->start, resource_size(r),
|
|
|
- dev_name(&pdev->dev))) {
|
|
|
- status = -EBUSY;
|
|
|
- goto free_master;
|
|
|
- }
|
|
|
|
|
|
- mcspi->base = ioremap(r->start, resource_size(r));
|
|
|
+ mcspi->base = devm_request_and_ioremap(&pdev->dev, r);
|
|
|
if (!mcspi->base) {
|
|
|
dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
|
|
|
status = -ENOMEM;
|
|
|
- goto release_region;
|
|
|
+ goto free_master;
|
|
|
}
|
|
|
|
|
|
mcspi->dev = &pdev->dev;
|
|
|
- INIT_WORK(&mcspi->work, omap2_mcspi_work);
|
|
|
|
|
|
- spin_lock_init(&mcspi->lock);
|
|
|
- INIT_LIST_HEAD(&mcspi->msg_queue);
|
|
|
- INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
|
|
|
+ INIT_LIST_HEAD(&mcspi->ctx.cs);
|
|
|
|
|
|
mcspi->dma_channels = kcalloc(master->num_chipselect,
|
|
|
sizeof(struct omap2_mcspi_dma),
|
|
|
GFP_KERNEL);
|
|
|
|
|
|
if (mcspi->dma_channels == NULL)
|
|
|
- goto unmap_io;
|
|
|
+ goto free_master;
|
|
|
|
|
|
for (i = 0; i < master->num_chipselect; i++) {
|
|
|
char dma_ch_name[14];
|
|
@@ -1224,6 +1191,8 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
|
|
|
if (status < 0)
|
|
|
goto dma_chnl_free;
|
|
|
|
|
|
+ pm_runtime_use_autosuspend(&pdev->dev);
|
|
|
+ pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
|
|
if (status || omap2_mcspi_master_setup(mcspi) < 0)
|
|
@@ -1241,23 +1210,17 @@ disable_pm:
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
dma_chnl_free:
|
|
|
kfree(mcspi->dma_channels);
|
|
|
-unmap_io:
|
|
|
- iounmap(mcspi->base);
|
|
|
-release_region:
|
|
|
- release_mem_region(r->start, resource_size(r));
|
|
|
free_master:
|
|
|
kfree(master);
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
return status;
|
|
|
}
|
|
|
|
|
|
-static int __exit omap2_mcspi_remove(struct platform_device *pdev)
|
|
|
+static int __devexit omap2_mcspi_remove(struct platform_device *pdev)
|
|
|
{
|
|
|
struct spi_master *master;
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
struct omap2_mcspi_dma *dma_channels;
|
|
|
- struct resource *r;
|
|
|
- void __iomem *base;
|
|
|
|
|
|
master = dev_get_drvdata(&pdev->dev);
|
|
|
mcspi = spi_master_get_devdata(master);
|
|
@@ -1265,14 +1228,9 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev)
|
|
|
|
|
|
omap2_mcspi_disable_clocks(mcspi);
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
- r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
- release_mem_region(r->start, resource_size(r));
|
|
|
|
|
|
- base = mcspi->base;
|
|
|
spi_unregister_master(master);
|
|
|
- iounmap(base);
|
|
|
kfree(dma_channels);
|
|
|
- destroy_workqueue(mcspi->wq);
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
|
|
return 0;
|
|
@@ -1291,13 +1249,12 @@ static int omap2_mcspi_resume(struct device *dev)
|
|
|
{
|
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
|
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
|
|
|
- struct omap2_mcspi_cs *cs;
|
|
|
+ struct omap2_mcspi_regs *ctx = &mcspi->ctx;
|
|
|
+ struct omap2_mcspi_cs *cs;
|
|
|
|
|
|
omap2_mcspi_enable_clocks(mcspi);
|
|
|
- list_for_each_entry(cs, &omap2_mcspi_ctx[master->bus_num - 1].cs,
|
|
|
- node) {
|
|
|
+ list_for_each_entry(cs, &ctx->cs, node) {
|
|
|
if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
|
|
|
-
|
|
|
/*
|
|
|
* We need to toggle CS state for OMAP take this
|
|
|
* change in account.
|
|
@@ -1327,21 +1284,9 @@ static struct platform_driver omap2_mcspi_driver = {
|
|
|
.pm = &omap2_mcspi_pm_ops,
|
|
|
.of_match_table = omap_mcspi_of_match,
|
|
|
},
|
|
|
- .remove = __exit_p(omap2_mcspi_remove),
|
|
|
+ .probe = omap2_mcspi_probe,
|
|
|
+ .remove = __devexit_p(omap2_mcspi_remove),
|
|
|
};
|
|
|
|
|
|
-
|
|
|
-static int __init omap2_mcspi_init(void)
|
|
|
-{
|
|
|
- return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
|
|
|
-}
|
|
|
-subsys_initcall(omap2_mcspi_init);
|
|
|
-
|
|
|
-static void __exit omap2_mcspi_exit(void)
|
|
|
-{
|
|
|
- platform_driver_unregister(&omap2_mcspi_driver);
|
|
|
-
|
|
|
-}
|
|
|
-module_exit(omap2_mcspi_exit);
|
|
|
-
|
|
|
+module_platform_driver(omap2_mcspi_driver);
|
|
|
MODULE_LICENSE("GPL");
|