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@@ -14,10 +14,6 @@
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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*/
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-/*
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- * Implementation of receive path.
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- */
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-
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#include "core.h"
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#include "core.h"
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/*
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/*
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@@ -27,10 +23,7 @@
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* MAC acknowledges BA status as long as it copies frames to host
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* MAC acknowledges BA status as long as it copies frames to host
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* buffer (or rx fifo). This can incorrectly acknowledge packets
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* buffer (or rx fifo). This can incorrectly acknowledge packets
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* to a sender if last desc is self-linked.
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* to a sender if last desc is self-linked.
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- *
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- * NOTE: Caller should hold the rxbuf lock.
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*/
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*/
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-
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static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
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static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
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{
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{
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struct ath_hal *ah = sc->sc_ah;
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struct ath_hal *ah = sc->sc_ah;
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@@ -40,19 +33,17 @@ static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
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ATH_RXBUF_RESET(bf);
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ATH_RXBUF_RESET(bf);
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ds = bf->bf_desc;
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ds = bf->bf_desc;
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- ds->ds_link = 0; /* link to null */
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+ ds->ds_link = 0; /* link to null */
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ds->ds_data = bf->bf_buf_addr;
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ds->ds_data = bf->bf_buf_addr;
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- /* XXX For RADAR?
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- * virtual addr of the beginning of the buffer. */
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+ /* virtual addr of the beginning of the buffer. */
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skb = bf->bf_mpdu;
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skb = bf->bf_mpdu;
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ASSERT(skb != NULL);
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ASSERT(skb != NULL);
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ds->ds_vdata = skb->data;
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ds->ds_vdata = skb->data;
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/* setup rx descriptors */
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/* setup rx descriptors */
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- ath9k_hw_setuprxdesc(ah,
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- ds,
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- skb_tailroom(skb), /* buffer size */
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+ ath9k_hw_setuprxdesc(ah, ds,
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+ skb_tailroom(skb), /* buffer size */
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0);
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0);
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if (sc->sc_rxlink == NULL)
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if (sc->sc_rxlink == NULL)
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@@ -64,8 +55,7 @@ static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
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ath9k_hw_rxena(ah);
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ath9k_hw_rxena(ah);
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}
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}
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-static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc,
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- u32 len)
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+static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc, u32 len)
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{
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{
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struct sk_buff *skb;
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struct sk_buff *skb;
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u32 off;
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u32 off;
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@@ -91,59 +81,154 @@ static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc,
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return skb;
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return skb;
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}
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}
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-static void ath_rx_requeue(struct ath_softc *sc, struct sk_buff *skb)
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+static void ath_rx_requeue(struct ath_softc *sc, struct ath_buf *bf)
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{
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{
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- struct ath_buf *bf = ATH_RX_CONTEXT(skb)->ctx_rxbuf;
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+ struct sk_buff *skb;
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ASSERT(bf != NULL);
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ASSERT(bf != NULL);
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- spin_lock_bh(&sc->sc_rxbuflock);
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- if (bf->bf_status & ATH_BUFSTATUS_STALE) {
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- /*
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- * This buffer is still held for hw acess.
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- * Mark it as free to be re-queued it later.
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- */
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- bf->bf_status |= ATH_BUFSTATUS_FREE;
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- } else {
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- /* XXX: we probably never enter here, remove after
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- * verification */
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- list_add_tail(&bf->list, &sc->sc_rxbuf);
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- ath_rx_buf_link(sc, bf);
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+ if (bf->bf_mpdu == NULL) {
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+ skb = ath_rxbuf_alloc(sc, sc->sc_rxbufsize);
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+ if (skb != NULL) {
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+ bf->bf_mpdu = skb;
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+ bf->bf_buf_addr = pci_map_single(sc->pdev, skb->data,
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+ skb_end_pointer(skb) - skb->head,
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+ PCI_DMA_FROMDEVICE);
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+ bf->bf_dmacontext = bf->bf_buf_addr;
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+
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+ }
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}
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}
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- spin_unlock_bh(&sc->sc_rxbuflock);
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+
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+ list_move_tail(&bf->list, &sc->sc_rxbuf);
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+ ath_rx_buf_link(sc, bf);
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+}
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+
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+
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+static int ath_rate2idx(struct ath_softc *sc, int rate)
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+{
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+ int i = 0, cur_band, n_rates;
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+ struct ieee80211_hw *hw = sc->hw;
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+
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+ cur_band = hw->conf.channel->band;
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+ n_rates = sc->sbands[cur_band].n_bitrates;
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+
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+ for (i = 0; i < n_rates; i++) {
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+ if (sc->sbands[cur_band].bitrates[i].bitrate == rate)
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+ break;
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+ }
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+
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+ /*
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+ * NB:mac80211 validates rx rate index against the supported legacy rate
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+ * index only (should be done against ht rates also), return the highest
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+ * legacy rate index for rx rate which does not match any one of the
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+ * supported basic and extended rates to make mac80211 happy.
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+ * The following hack will be cleaned up once the issue with
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+ * the rx rate index validation in mac80211 is fixed.
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+ */
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+ if (i == n_rates)
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+ return n_rates - 1;
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+
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+ return i;
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}
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}
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/*
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/*
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- * The skb indicated to upper stack won't be returned to us.
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- * So we have to allocate a new one and queue it by ourselves.
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+ * For Decrypt or Demic errors, we only mark packet status here and always push
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+ * up the frame up to let mac80211 handle the actual error case, be it no
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+ * decryption key or real decryption error. This let us keep statistics there.
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*/
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*/
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-static int ath_rx_indicate(struct ath_softc *sc,
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- struct sk_buff *skb,
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- struct ath_recv_status *status,
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- u16 keyix)
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+static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds,
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+ struct ieee80211_rx_status *rx_status, bool *decrypt_error,
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+ struct ath_softc *sc)
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{
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{
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- struct ath_buf *bf = ATH_RX_CONTEXT(skb)->ctx_rxbuf;
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- struct sk_buff *nskb;
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- int type;
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-
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- /* indicate frame to the stack, which will free the old skb. */
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- type = _ath_rx_indicate(sc, skb, status, keyix);
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-
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- /* allocate a new skb and queue it to for H/W processing */
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- nskb = ath_rxbuf_alloc(sc, sc->sc_rxbufsize);
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- if (nskb != NULL) {
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- bf->bf_mpdu = nskb;
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- bf->bf_buf_addr = pci_map_single(sc->pdev, nskb->data,
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- skb_end_pointer(nskb) - nskb->head,
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- PCI_DMA_FROMDEVICE);
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- bf->bf_dmacontext = bf->bf_buf_addr;
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- ATH_RX_CONTEXT(nskb)->ctx_rxbuf = bf;
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+ struct ieee80211_hdr *hdr;
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+ int ratekbps;
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+ u8 ratecode;
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+ __le16 fc;
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+
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+ hdr = (struct ieee80211_hdr *)skb->data;
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+ fc = hdr->frame_control;
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+ memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
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+
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+ if (ds->ds_rxstat.rs_more) {
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+ /*
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+ * Frame spans multiple descriptors; this cannot happen yet
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+ * as we don't support jumbograms. If not in monitor mode,
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+ * discard the frame. Enable this if you want to see
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+ * error frames in Monitor mode.
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+ */
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+ if (sc->sc_ah->ah_opmode != ATH9K_M_MONITOR)
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+ goto rx_next;
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+ } else if (ds->ds_rxstat.rs_status != 0) {
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+ if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC)
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+ rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
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+ if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY)
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+ goto rx_next;
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- /* queue the new wbuf to H/W */
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- ath_rx_requeue(sc, nskb);
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+ if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT) {
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+ *decrypt_error = true;
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+ } else if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC) {
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+ if (ieee80211_is_ctl(fc))
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+ /*
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+ * Sometimes, we get invalid
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+ * MIC failures on valid control frames.
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+ * Remove these mic errors.
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+ */
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+ ds->ds_rxstat.rs_status &= ~ATH9K_RXERR_MIC;
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+ else
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+ rx_status->flag |= RX_FLAG_MMIC_ERROR;
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+ }
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+ /*
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+ * Reject error frames with the exception of
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+ * decryption and MIC failures. For monitor mode,
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+ * we also ignore the CRC error.
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+ */
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+ if (sc->sc_ah->ah_opmode == ATH9K_M_MONITOR) {
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+ if (ds->ds_rxstat.rs_status &
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+ ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
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+ ATH9K_RXERR_CRC))
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+ goto rx_next;
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+ } else {
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+ if (ds->ds_rxstat.rs_status &
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+ ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
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+ goto rx_next;
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+ }
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+ }
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}
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}
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- return type;
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+ ratecode = ds->ds_rxstat.rs_rate;
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+ ratekbps = sc->sc_hwmap[ratecode].rateKbps;
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+
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+ /* HT rate */
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+ if (ratecode & 0x80) {
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+ if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040)
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+ ratekbps = (ratekbps * 27) / 13;
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+ if (ds->ds_rxstat.rs_flags & ATH9K_RX_GI)
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+ ratekbps = (ratekbps * 10) / 9;
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+ }
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+
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+ rx_status->mactime = ath_extend_tsf(sc, ds->ds_rxstat.rs_tstamp);
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+ rx_status->band = sc->hw->conf.channel->band;
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+ rx_status->freq = sc->hw->conf.channel->center_freq;
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+ rx_status->noise = sc->sc_ani.sc_noise_floor;
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+ rx_status->signal = rx_status->noise + ds->ds_rxstat.rs_rssi;
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+ rx_status->rate_idx = ath_rate2idx(sc, (ratekbps / 100));
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+ rx_status->antenna = ds->ds_rxstat.rs_antenna;
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+
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+ /* at 45 you will be able to use MCS 15 reliably. A more elaborate
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+ * scheme can be used here but it requires tables of SNR/throughput for
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+ * each possible mode used. */
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+ rx_status->qual = ds->ds_rxstat.rs_rssi * 100 / 45;
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+
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+ /* rssi can be more than 45 though, anything above that
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+ * should be considered at 100% */
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+ if (rx_status->qual > 100)
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+ rx_status->qual = 100;
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+
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+ rx_status->flag |= RX_FLAG_TSFT;
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+
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+ return 1;
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+rx_next:
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+ return 0;
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}
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}
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static void ath_opmode_init(struct ath_softc *sc)
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static void ath_opmode_init(struct ath_softc *sc)
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@@ -185,12 +270,6 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
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sc->sc_flags &= ~SC_OP_RXFLUSH;
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sc->sc_flags &= ~SC_OP_RXFLUSH;
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spin_lock_init(&sc->sc_rxbuflock);
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spin_lock_init(&sc->sc_rxbuflock);
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- /*
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- * Cisco's VPN software requires that drivers be able to
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- * receive encapsulated frames that are larger than the MTU.
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- * Since we can't be sure how large a frame we'll get, setup
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- * to handle the larges on possible.
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- */
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sc->sc_rxbufsize = roundup(IEEE80211_MAX_MPDU_LEN,
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sc->sc_rxbufsize = roundup(IEEE80211_MAX_MPDU_LEN,
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min(sc->sc_cachelsz,
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min(sc->sc_cachelsz,
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(u16)64));
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(u16)64));
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@@ -209,8 +288,6 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
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break;
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break;
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}
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}
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- /* Pre-allocate a wbuf for each rx buffer */
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-
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list_for_each_entry(bf, &sc->sc_rxbuf, list) {
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list_for_each_entry(bf, &sc->sc_rxbuf, list) {
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skb = ath_rxbuf_alloc(sc, sc->sc_rxbufsize);
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skb = ath_rxbuf_alloc(sc, sc->sc_rxbufsize);
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if (skb == NULL) {
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if (skb == NULL) {
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@@ -223,7 +300,6 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
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skb_end_pointer(skb) - skb->head,
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skb_end_pointer(skb) - skb->head,
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PCI_DMA_FROMDEVICE);
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PCI_DMA_FROMDEVICE);
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bf->bf_dmacontext = bf->bf_buf_addr;
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bf->bf_dmacontext = bf->bf_buf_addr;
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- ATH_RX_CONTEXT(skb)->ctx_rxbuf = bf;
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}
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}
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sc->sc_rxlink = NULL;
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sc->sc_rxlink = NULL;
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@@ -235,8 +311,6 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
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return error;
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return error;
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}
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}
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-/* Reclaim all rx queue resources */
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-
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void ath_rx_cleanup(struct ath_softc *sc)
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void ath_rx_cleanup(struct ath_softc *sc)
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{
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{
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struct sk_buff *skb;
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struct sk_buff *skb;
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@@ -248,8 +322,6 @@ void ath_rx_cleanup(struct ath_softc *sc)
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dev_kfree_skb(skb);
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dev_kfree_skb(skb);
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}
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}
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- /* cleanup rx descriptors */
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-
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if (sc->sc_rxdma.dd_desc_len != 0)
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if (sc->sc_rxdma.dd_desc_len != 0)
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ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
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ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
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}
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}
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@@ -297,20 +369,19 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
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}
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}
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if (sc->sc_ah->ah_opmode == ATH9K_M_STA ||
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if (sc->sc_ah->ah_opmode == ATH9K_M_STA ||
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- sc->sc_ah->ah_opmode == ATH9K_M_IBSS)
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+ sc->sc_ah->ah_opmode == ATH9K_M_IBSS)
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rfilt |= ATH9K_RX_FILTER_BEACON;
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rfilt |= ATH9K_RX_FILTER_BEACON;
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/* If in HOSTAP mode, want to enable reception of PSPOLL frames
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/* If in HOSTAP mode, want to enable reception of PSPOLL frames
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& beacon frames */
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& beacon frames */
|
|
if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP)
|
|
if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP)
|
|
rfilt |= (ATH9K_RX_FILTER_BEACON | ATH9K_RX_FILTER_PSPOLL);
|
|
rfilt |= (ATH9K_RX_FILTER_BEACON | ATH9K_RX_FILTER_PSPOLL);
|
|
|
|
+
|
|
return rfilt;
|
|
return rfilt;
|
|
|
|
|
|
#undef RX_FILTER_PRESERVE
|
|
#undef RX_FILTER_PRESERVE
|
|
}
|
|
}
|
|
|
|
|
|
-/* Enable the receive h/w following a reset. */
|
|
|
|
-
|
|
|
|
int ath_startrecv(struct ath_softc *sc)
|
|
int ath_startrecv(struct ath_softc *sc)
|
|
{
|
|
{
|
|
struct ath_hal *ah = sc->sc_ah;
|
|
struct ath_hal *ah = sc->sc_ah;
|
|
@@ -322,21 +393,6 @@ int ath_startrecv(struct ath_softc *sc)
|
|
|
|
|
|
sc->sc_rxlink = NULL;
|
|
sc->sc_rxlink = NULL;
|
|
list_for_each_entry_safe(bf, tbf, &sc->sc_rxbuf, list) {
|
|
list_for_each_entry_safe(bf, tbf, &sc->sc_rxbuf, list) {
|
|
- if (bf->bf_status & ATH_BUFSTATUS_STALE) {
|
|
|
|
- /* restarting h/w, no need for holding descriptors */
|
|
|
|
- bf->bf_status &= ~ATH_BUFSTATUS_STALE;
|
|
|
|
- /*
|
|
|
|
- * Upper layer may not be done with the frame yet so
|
|
|
|
- * we can't just re-queue it to hardware. Remove it
|
|
|
|
- * from h/w queue. It'll be re-queued when upper layer
|
|
|
|
- * returns the frame and ath_rx_requeue_mpdu is called.
|
|
|
|
- */
|
|
|
|
- if (!(bf->bf_status & ATH_BUFSTATUS_FREE)) {
|
|
|
|
- list_del(&bf->list);
|
|
|
|
- continue;
|
|
|
|
- }
|
|
|
|
- }
|
|
|
|
- /* chain descriptors */
|
|
|
|
ath_rx_buf_link(sc, bf);
|
|
ath_rx_buf_link(sc, bf);
|
|
}
|
|
}
|
|
|
|
|
|
@@ -346,120 +402,69 @@ int ath_startrecv(struct ath_softc *sc)
|
|
|
|
|
|
bf = list_first_entry(&sc->sc_rxbuf, struct ath_buf, list);
|
|
bf = list_first_entry(&sc->sc_rxbuf, struct ath_buf, list);
|
|
ath9k_hw_putrxbuf(ah, bf->bf_daddr);
|
|
ath9k_hw_putrxbuf(ah, bf->bf_daddr);
|
|
- ath9k_hw_rxena(ah); /* enable recv descriptors */
|
|
|
|
|
|
+ ath9k_hw_rxena(ah);
|
|
|
|
|
|
start_recv:
|
|
start_recv:
|
|
spin_unlock_bh(&sc->sc_rxbuflock);
|
|
spin_unlock_bh(&sc->sc_rxbuflock);
|
|
- ath_opmode_init(sc); /* set filters, etc. */
|
|
|
|
- ath9k_hw_startpcureceive(ah); /* re-enable PCU/DMA engine */
|
|
|
|
|
|
+ ath_opmode_init(sc);
|
|
|
|
+ ath9k_hw_startpcureceive(ah);
|
|
|
|
+
|
|
return 0;
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
|
|
-/* Disable the receive h/w in preparation for a reset. */
|
|
|
|
-
|
|
|
|
bool ath_stoprecv(struct ath_softc *sc)
|
|
bool ath_stoprecv(struct ath_softc *sc)
|
|
{
|
|
{
|
|
struct ath_hal *ah = sc->sc_ah;
|
|
struct ath_hal *ah = sc->sc_ah;
|
|
- u64 tsf;
|
|
|
|
bool stopped;
|
|
bool stopped;
|
|
|
|
|
|
- ath9k_hw_stoppcurecv(ah); /* disable PCU */
|
|
|
|
- ath9k_hw_setrxfilter(ah, 0); /* clear recv filter */
|
|
|
|
- stopped = ath9k_hw_stopdmarecv(ah); /* disable DMA engine */
|
|
|
|
- mdelay(3); /* 3ms is long enough for 1 frame */
|
|
|
|
- tsf = ath9k_hw_gettsf64(ah);
|
|
|
|
- sc->sc_rxlink = NULL; /* just in case */
|
|
|
|
|
|
+ ath9k_hw_stoppcurecv(ah);
|
|
|
|
+ ath9k_hw_setrxfilter(ah, 0);
|
|
|
|
+ stopped = ath9k_hw_stopdmarecv(ah);
|
|
|
|
+ mdelay(3); /* 3ms is long enough for 1 frame */
|
|
|
|
+ sc->sc_rxlink = NULL;
|
|
|
|
+
|
|
return stopped;
|
|
return stopped;
|
|
}
|
|
}
|
|
|
|
|
|
-/* Flush receive queue */
|
|
|
|
-
|
|
|
|
void ath_flushrecv(struct ath_softc *sc)
|
|
void ath_flushrecv(struct ath_softc *sc)
|
|
{
|
|
{
|
|
- /*
|
|
|
|
- * ath_rx_tasklet may be used to handle rx interrupt and flush receive
|
|
|
|
- * queue at the same time. Use a lock to serialize the access of rx
|
|
|
|
- * queue.
|
|
|
|
- * ath_rx_tasklet cannot hold the spinlock while indicating packets.
|
|
|
|
- * Instead, do not claim the spinlock but check for a flush in
|
|
|
|
- * progress (see references to sc_rxflush)
|
|
|
|
- */
|
|
|
|
spin_lock_bh(&sc->sc_rxflushlock);
|
|
spin_lock_bh(&sc->sc_rxflushlock);
|
|
sc->sc_flags |= SC_OP_RXFLUSH;
|
|
sc->sc_flags |= SC_OP_RXFLUSH;
|
|
-
|
|
|
|
ath_rx_tasklet(sc, 1);
|
|
ath_rx_tasklet(sc, 1);
|
|
-
|
|
|
|
sc->sc_flags &= ~SC_OP_RXFLUSH;
|
|
sc->sc_flags &= ~SC_OP_RXFLUSH;
|
|
spin_unlock_bh(&sc->sc_rxflushlock);
|
|
spin_unlock_bh(&sc->sc_rxflushlock);
|
|
}
|
|
}
|
|
|
|
|
|
-/* Process receive queue, as well as LED, etc. */
|
|
|
|
-
|
|
|
|
int ath_rx_tasklet(struct ath_softc *sc, int flush)
|
|
int ath_rx_tasklet(struct ath_softc *sc, int flush)
|
|
{
|
|
{
|
|
#define PA2DESC(_sc, _pa) \
|
|
#define PA2DESC(_sc, _pa) \
|
|
((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
|
|
((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
|
|
((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
|
|
((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
|
|
|
|
|
|
- struct ath_buf *bf, *bf_held = NULL;
|
|
|
|
|
|
+ struct ath_buf *bf;
|
|
struct ath_desc *ds;
|
|
struct ath_desc *ds;
|
|
- struct ieee80211_hdr *hdr;
|
|
|
|
struct sk_buff *skb = NULL;
|
|
struct sk_buff *skb = NULL;
|
|
- struct ath_recv_status rx_status;
|
|
|
|
|
|
+ struct ieee80211_rx_status rx_status;
|
|
struct ath_hal *ah = sc->sc_ah;
|
|
struct ath_hal *ah = sc->sc_ah;
|
|
- int type, rx_processed = 0;
|
|
|
|
- u32 phyerr;
|
|
|
|
- u8 chainreset = 0;
|
|
|
|
- int retval;
|
|
|
|
- __le16 fc;
|
|
|
|
|
|
+ struct ieee80211_hdr *hdr;
|
|
|
|
+ int hdrlen, padsize, retval;
|
|
|
|
+ bool decrypt_error = false;
|
|
|
|
+ u8 keyix;
|
|
|
|
+
|
|
|
|
+ spin_lock_bh(&sc->sc_rxbuflock);
|
|
|
|
|
|
do {
|
|
do {
|
|
/* If handling rx interrupt and flush is in progress => exit */
|
|
/* If handling rx interrupt and flush is in progress => exit */
|
|
if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
|
|
if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
|
|
break;
|
|
break;
|
|
|
|
|
|
- spin_lock_bh(&sc->sc_rxbuflock);
|
|
|
|
if (list_empty(&sc->sc_rxbuf)) {
|
|
if (list_empty(&sc->sc_rxbuf)) {
|
|
sc->sc_rxlink = NULL;
|
|
sc->sc_rxlink = NULL;
|
|
- spin_unlock_bh(&sc->sc_rxbuflock);
|
|
|
|
break;
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
bf = list_first_entry(&sc->sc_rxbuf, struct ath_buf, list);
|
|
bf = list_first_entry(&sc->sc_rxbuf, struct ath_buf, list);
|
|
-
|
|
|
|
- /*
|
|
|
|
- * There is a race condition that BH gets scheduled after sw
|
|
|
|
- * writes RxE and before hw re-load the last descriptor to get
|
|
|
|
- * the newly chained one. Software must keep the last DONE
|
|
|
|
- * descriptor as a holding descriptor - software does so by
|
|
|
|
- * marking it with the STALE flag.
|
|
|
|
- */
|
|
|
|
- if (bf->bf_status & ATH_BUFSTATUS_STALE) {
|
|
|
|
- bf_held = bf;
|
|
|
|
- if (list_is_last(&bf_held->list, &sc->sc_rxbuf)) {
|
|
|
|
- /*
|
|
|
|
- * The holding descriptor is the last
|
|
|
|
- * descriptor in queue. It's safe to
|
|
|
|
- * remove the last holding descriptor
|
|
|
|
- * in BH context.
|
|
|
|
- */
|
|
|
|
- list_del(&bf_held->list);
|
|
|
|
- bf_held->bf_status &= ~ATH_BUFSTATUS_STALE;
|
|
|
|
- sc->sc_rxlink = NULL;
|
|
|
|
-
|
|
|
|
- if (bf_held->bf_status & ATH_BUFSTATUS_FREE) {
|
|
|
|
- list_add_tail(&bf_held->list,
|
|
|
|
- &sc->sc_rxbuf);
|
|
|
|
- ath_rx_buf_link(sc, bf_held);
|
|
|
|
- }
|
|
|
|
- spin_unlock_bh(&sc->sc_rxbuflock);
|
|
|
|
- break;
|
|
|
|
- }
|
|
|
|
- bf = list_entry(bf->list.next, struct ath_buf, list);
|
|
|
|
- }
|
|
|
|
-
|
|
|
|
ds = bf->bf_desc;
|
|
ds = bf->bf_desc;
|
|
- ++rx_processed;
|
|
|
|
|
|
|
|
/*
|
|
/*
|
|
* Must provide the virtual address of the current
|
|
* Must provide the virtual address of the current
|
|
@@ -472,8 +477,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
|
|
* on. All this is necessary because of our use of
|
|
* on. All this is necessary because of our use of
|
|
* a self-linked list to avoid rx overruns.
|
|
* a self-linked list to avoid rx overruns.
|
|
*/
|
|
*/
|
|
- retval = ath9k_hw_rxprocdesc(ah,
|
|
|
|
- ds,
|
|
|
|
|
|
+ retval = ath9k_hw_rxprocdesc(ah, ds,
|
|
bf->bf_daddr,
|
|
bf->bf_daddr,
|
|
PA2DESC(sc, ds->ds_link),
|
|
PA2DESC(sc, ds->ds_link),
|
|
0);
|
|
0);
|
|
@@ -482,7 +486,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
|
|
struct ath_desc *tds;
|
|
struct ath_desc *tds;
|
|
|
|
|
|
if (list_is_last(&bf->list, &sc->sc_rxbuf)) {
|
|
if (list_is_last(&bf->list, &sc->sc_rxbuf)) {
|
|
- spin_unlock_bh(&sc->sc_rxbuflock);
|
|
|
|
|
|
+ sc->sc_rxlink = NULL;
|
|
break;
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
@@ -500,215 +504,70 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
|
|
*/
|
|
*/
|
|
|
|
|
|
tds = tbf->bf_desc;
|
|
tds = tbf->bf_desc;
|
|
- retval = ath9k_hw_rxprocdesc(ah,
|
|
|
|
- tds, tbf->bf_daddr,
|
|
|
|
- PA2DESC(sc, tds->ds_link), 0);
|
|
|
|
|
|
+ retval = ath9k_hw_rxprocdesc(ah, tds, tbf->bf_daddr,
|
|
|
|
+ PA2DESC(sc, tds->ds_link), 0);
|
|
if (retval == -EINPROGRESS) {
|
|
if (retval == -EINPROGRESS) {
|
|
- spin_unlock_bh(&sc->sc_rxbuflock);
|
|
|
|
break;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
- /* XXX: we do not support frames spanning
|
|
|
|
- * multiple descriptors */
|
|
|
|
- bf->bf_status |= ATH_BUFSTATUS_DONE;
|
|
|
|
-
|
|
|
|
skb = bf->bf_mpdu;
|
|
skb = bf->bf_mpdu;
|
|
- if (skb == NULL) { /* XXX ??? can this happen */
|
|
|
|
- spin_unlock_bh(&sc->sc_rxbuflock);
|
|
|
|
|
|
+ if (!skb)
|
|
continue;
|
|
continue;
|
|
- }
|
|
|
|
- /*
|
|
|
|
- * Now we know it's a completed frame, we can indicate the
|
|
|
|
- * frame. Remove the previous holding descriptor and leave
|
|
|
|
- * this one in the queue as the new holding descriptor.
|
|
|
|
- */
|
|
|
|
- if (bf_held) {
|
|
|
|
- list_del(&bf_held->list);
|
|
|
|
- bf_held->bf_status &= ~ATH_BUFSTATUS_STALE;
|
|
|
|
- if (bf_held->bf_status & ATH_BUFSTATUS_FREE) {
|
|
|
|
- list_add_tail(&bf_held->list, &sc->sc_rxbuf);
|
|
|
|
- /* try to requeue this descriptor */
|
|
|
|
- ath_rx_buf_link(sc, bf_held);
|
|
|
|
- }
|
|
|
|
- }
|
|
|
|
|
|
|
|
- bf->bf_status |= ATH_BUFSTATUS_STALE;
|
|
|
|
- bf_held = bf;
|
|
|
|
/*
|
|
/*
|
|
- * Release the lock here in case ieee80211_input() return
|
|
|
|
- * the frame immediately by calling ath_rx_mpdu_requeue().
|
|
|
|
|
|
+ * If we're asked to flush receive queue, directly
|
|
|
|
+ * chain it back at the queue without processing it.
|
|
*/
|
|
*/
|
|
- spin_unlock_bh(&sc->sc_rxbuflock);
|
|
|
|
-
|
|
|
|
- if (flush) {
|
|
|
|
- /*
|
|
|
|
- * If we're asked to flush receive queue, directly
|
|
|
|
- * chain it back at the queue without processing it.
|
|
|
|
- */
|
|
|
|
|
|
+ if (flush)
|
|
goto rx_next;
|
|
goto rx_next;
|
|
- }
|
|
|
|
|
|
|
|
- hdr = (struct ieee80211_hdr *)skb->data;
|
|
|
|
- fc = hdr->frame_control;
|
|
|
|
- memset(&rx_status, 0, sizeof(struct ath_recv_status));
|
|
|
|
-
|
|
|
|
- if (ds->ds_rxstat.rs_more) {
|
|
|
|
- /*
|
|
|
|
- * Frame spans multiple descriptors; this
|
|
|
|
- * cannot happen yet as we don't support
|
|
|
|
- * jumbograms. If not in monitor mode,
|
|
|
|
- * discard the frame.
|
|
|
|
- */
|
|
|
|
-#ifndef ERROR_FRAMES
|
|
|
|
- /*
|
|
|
|
- * Enable this if you want to see
|
|
|
|
- * error frames in Monitor mode.
|
|
|
|
- */
|
|
|
|
- if (sc->sc_ah->ah_opmode != ATH9K_M_MONITOR)
|
|
|
|
- goto rx_next;
|
|
|
|
-#endif
|
|
|
|
- /* fall thru for monitor mode handling... */
|
|
|
|
- } else if (ds->ds_rxstat.rs_status != 0) {
|
|
|
|
- if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC)
|
|
|
|
- rx_status.flags |= ATH_RX_FCS_ERROR;
|
|
|
|
- if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY) {
|
|
|
|
- phyerr = ds->ds_rxstat.rs_phyerr & 0x1f;
|
|
|
|
- goto rx_next;
|
|
|
|
- }
|
|
|
|
|
|
+ if (!ds->ds_rxstat.rs_datalen)
|
|
|
|
+ goto rx_next;
|
|
|
|
|
|
- if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT) {
|
|
|
|
- /*
|
|
|
|
- * Decrypt error. We only mark packet status
|
|
|
|
- * here and always push up the frame up to let
|
|
|
|
- * mac80211 handle the actual error case, be
|
|
|
|
- * it no decryption key or real decryption
|
|
|
|
- * error. This let us keep statistics there.
|
|
|
|
- */
|
|
|
|
- rx_status.flags |= ATH_RX_DECRYPT_ERROR;
|
|
|
|
- } else if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC) {
|
|
|
|
- /*
|
|
|
|
- * Demic error. We only mark frame status here
|
|
|
|
- * and always push up the frame up to let
|
|
|
|
- * mac80211 handle the actual error case. This
|
|
|
|
- * let us keep statistics there. Hardware may
|
|
|
|
- * post a false-positive MIC error.
|
|
|
|
- */
|
|
|
|
- if (ieee80211_is_ctl(fc))
|
|
|
|
- /*
|
|
|
|
- * Sometimes, we get invalid
|
|
|
|
- * MIC failures on valid control frames.
|
|
|
|
- * Remove these mic errors.
|
|
|
|
- */
|
|
|
|
- ds->ds_rxstat.rs_status &=
|
|
|
|
- ~ATH9K_RXERR_MIC;
|
|
|
|
- else
|
|
|
|
- rx_status.flags |= ATH_RX_MIC_ERROR;
|
|
|
|
- }
|
|
|
|
- /*
|
|
|
|
- * Reject error frames with the exception of
|
|
|
|
- * decryption and MIC failures. For monitor mode,
|
|
|
|
- * we also ignore the CRC error.
|
|
|
|
- */
|
|
|
|
- if (sc->sc_ah->ah_opmode == ATH9K_M_MONITOR) {
|
|
|
|
- if (ds->ds_rxstat.rs_status &
|
|
|
|
- ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
|
|
|
|
- ATH9K_RXERR_CRC))
|
|
|
|
- goto rx_next;
|
|
|
|
- } else {
|
|
|
|
- if (ds->ds_rxstat.rs_status &
|
|
|
|
- ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
|
|
|
|
- goto rx_next;
|
|
|
|
- }
|
|
|
|
- }
|
|
|
|
- }
|
|
|
|
- /*
|
|
|
|
- * The status portion of the descriptor could get corrupted.
|
|
|
|
- */
|
|
|
|
|
|
+ /* The status portion of the descriptor could get corrupted. */
|
|
if (sc->sc_rxbufsize < ds->ds_rxstat.rs_datalen)
|
|
if (sc->sc_rxbufsize < ds->ds_rxstat.rs_datalen)
|
|
goto rx_next;
|
|
goto rx_next;
|
|
- /*
|
|
|
|
- * Sync and unmap the frame. At this point we're
|
|
|
|
- * committed to passing the sk_buff somewhere so
|
|
|
|
- * clear buf_skb; this means a new sk_buff must be
|
|
|
|
- * allocated when the rx descriptor is setup again
|
|
|
|
- * to receive another frame.
|
|
|
|
- */
|
|
|
|
- skb_put(skb, ds->ds_rxstat.rs_datalen);
|
|
|
|
- skb->protocol = cpu_to_be16(ETH_P_CONTROL);
|
|
|
|
- rx_status.tsf = ath_extend_tsf(sc, ds->ds_rxstat.rs_tstamp);
|
|
|
|
- rx_status.rateieee =
|
|
|
|
- sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate;
|
|
|
|
- rx_status.rateKbps =
|
|
|
|
- sc->sc_hwmap[ds->ds_rxstat.rs_rate].rateKbps;
|
|
|
|
- rx_status.ratecode = ds->ds_rxstat.rs_rate;
|
|
|
|
-
|
|
|
|
- /* HT rate */
|
|
|
|
- if (rx_status.ratecode & 0x80) {
|
|
|
|
- /* TODO - add table to avoid division */
|
|
|
|
- if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) {
|
|
|
|
- rx_status.flags |= ATH_RX_40MHZ;
|
|
|
|
- rx_status.rateKbps =
|
|
|
|
- (rx_status.rateKbps * 27) / 13;
|
|
|
|
- }
|
|
|
|
- if (ds->ds_rxstat.rs_flags & ATH9K_RX_GI)
|
|
|
|
- rx_status.rateKbps =
|
|
|
|
- (rx_status.rateKbps * 10) / 9;
|
|
|
|
- else
|
|
|
|
- rx_status.flags |= ATH_RX_SHORT_GI;
|
|
|
|
- }
|
|
|
|
|
|
|
|
- /* sc_noise_floor is only available when the station
|
|
|
|
- attaches to an AP, so we use a default value
|
|
|
|
- if we are not yet attached. */
|
|
|
|
- rx_status.abs_rssi =
|
|
|
|
- ds->ds_rxstat.rs_rssi + sc->sc_ani.sc_noise_floor;
|
|
|
|
|
|
+ if (!ath_rx_prepare(skb, ds, &rx_status, &decrypt_error, sc))
|
|
|
|
+ goto rx_next;
|
|
|
|
|
|
- pci_dma_sync_single_for_cpu(sc->pdev,
|
|
|
|
- bf->bf_buf_addr,
|
|
|
|
|
|
+ /* Sync and unmap the frame */
|
|
|
|
+ pci_dma_sync_single_for_cpu(sc->pdev, bf->bf_buf_addr,
|
|
skb_tailroom(skb),
|
|
skb_tailroom(skb),
|
|
PCI_DMA_FROMDEVICE);
|
|
PCI_DMA_FROMDEVICE);
|
|
- pci_unmap_single(sc->pdev,
|
|
|
|
- bf->bf_buf_addr,
|
|
|
|
|
|
+ pci_unmap_single(sc->pdev, bf->bf_buf_addr,
|
|
sc->sc_rxbufsize,
|
|
sc->sc_rxbufsize,
|
|
PCI_DMA_FROMDEVICE);
|
|
PCI_DMA_FROMDEVICE);
|
|
|
|
|
|
- /* XXX: Ah! make me more readable, use a helper */
|
|
|
|
- if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
|
|
|
|
- if (ds->ds_rxstat.rs_moreaggr == 0) {
|
|
|
|
- rx_status.rssictl[0] =
|
|
|
|
- ds->ds_rxstat.rs_rssi_ctl0;
|
|
|
|
- rx_status.rssictl[1] =
|
|
|
|
- ds->ds_rxstat.rs_rssi_ctl1;
|
|
|
|
- rx_status.rssictl[2] =
|
|
|
|
- ds->ds_rxstat.rs_rssi_ctl2;
|
|
|
|
- rx_status.rssi = ds->ds_rxstat.rs_rssi;
|
|
|
|
- if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) {
|
|
|
|
- rx_status.rssiextn[0] =
|
|
|
|
- ds->ds_rxstat.rs_rssi_ext0;
|
|
|
|
- rx_status.rssiextn[1] =
|
|
|
|
- ds->ds_rxstat.rs_rssi_ext1;
|
|
|
|
- rx_status.rssiextn[2] =
|
|
|
|
- ds->ds_rxstat.rs_rssi_ext2;
|
|
|
|
- rx_status.flags |=
|
|
|
|
- ATH_RX_RSSI_EXTN_VALID;
|
|
|
|
- }
|
|
|
|
- rx_status.flags |= ATH_RX_RSSI_VALID |
|
|
|
|
- ATH_RX_CHAIN_RSSI_VALID;
|
|
|
|
- }
|
|
|
|
- } else {
|
|
|
|
- /*
|
|
|
|
- * Need to insert the "combined" rssi into the
|
|
|
|
- * status structure for upper layer processing
|
|
|
|
- */
|
|
|
|
- rx_status.rssi = ds->ds_rxstat.rs_rssi;
|
|
|
|
- rx_status.flags |= ATH_RX_RSSI_VALID;
|
|
|
|
|
|
+ skb_put(skb, ds->ds_rxstat.rs_datalen);
|
|
|
|
+ skb->protocol = cpu_to_be16(ETH_P_CONTROL);
|
|
|
|
+
|
|
|
|
+ /* see if any padding is done by the hw and remove it */
|
|
|
|
+ hdr = (struct ieee80211_hdr *)skb->data;
|
|
|
|
+ hdrlen = ieee80211_get_hdrlen_from_skb(skb);
|
|
|
|
+
|
|
|
|
+ if (hdrlen & 3) {
|
|
|
|
+ padsize = hdrlen % 4;
|
|
|
|
+ memmove(skb->data + padsize, skb->data, hdrlen);
|
|
|
|
+ skb_pull(skb, padsize);
|
|
}
|
|
}
|
|
|
|
|
|
- /* Pass frames up to the stack. */
|
|
|
|
|
|
+ keyix = ds->ds_rxstat.rs_keyix;
|
|
|
|
|
|
- type = ath_rx_indicate(sc, skb,
|
|
|
|
- &rx_status, ds->ds_rxstat.rs_keyix);
|
|
|
|
|
|
+ if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error) {
|
|
|
|
+ rx_status.flag |= RX_FLAG_DECRYPTED;
|
|
|
|
+ } else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED)
|
|
|
|
+ && !decrypt_error && skb->len >= hdrlen + 4) {
|
|
|
|
+ keyix = skb->data[hdrlen + 3] >> 6;
|
|
|
|
+
|
|
|
|
+ if (test_bit(keyix, sc->sc_keymap))
|
|
|
|
+ rx_status.flag |= RX_FLAG_DECRYPTED;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ /* Send the frame to mac80211 */
|
|
|
|
+ __ieee80211_rx(sc->hw, skb, &rx_status);
|
|
|
|
+ bf->bf_mpdu = NULL;
|
|
|
|
|
|
/*
|
|
/*
|
|
* change the default rx antenna if rx diversity chooses the
|
|
* change the default rx antenna if rx diversity chooses the
|
|
@@ -716,37 +575,15 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
|
|
*/
|
|
*/
|
|
if (sc->sc_defant != ds->ds_rxstat.rs_antenna) {
|
|
if (sc->sc_defant != ds->ds_rxstat.rs_antenna) {
|
|
if (++sc->sc_rxotherant >= 3)
|
|
if (++sc->sc_rxotherant >= 3)
|
|
- ath_setdefantenna(sc,
|
|
|
|
- ds->ds_rxstat.rs_antenna);
|
|
|
|
|
|
+ ath_setdefantenna(sc, ds->ds_rxstat.rs_antenna);
|
|
} else {
|
|
} else {
|
|
sc->sc_rxotherant = 0;
|
|
sc->sc_rxotherant = 0;
|
|
}
|
|
}
|
|
-
|
|
|
|
-#ifdef CONFIG_SLOW_ANT_DIV
|
|
|
|
- if ((rx_status.flags & ATH_RX_RSSI_VALID) &&
|
|
|
|
- ieee80211_is_beacon(fc)) {
|
|
|
|
- ath_slow_ant_div(&sc->sc_antdiv, hdr, &ds->ds_rxstat);
|
|
|
|
- }
|
|
|
|
-#endif
|
|
|
|
- /*
|
|
|
|
- * For frames successfully indicated, the buffer will be
|
|
|
|
- * returned to us by upper layers by calling
|
|
|
|
- * ath_rx_mpdu_requeue, either synchronusly or asynchronously.
|
|
|
|
- * So we don't want to do it here in this loop.
|
|
|
|
- */
|
|
|
|
- continue;
|
|
|
|
-
|
|
|
|
rx_next:
|
|
rx_next:
|
|
- bf->bf_status |= ATH_BUFSTATUS_FREE;
|
|
|
|
- } while (TRUE);
|
|
|
|
-
|
|
|
|
- if (chainreset) {
|
|
|
|
- DPRINTF(sc, ATH_DBG_CONFIG,
|
|
|
|
- "%s: Reset rx chain mask. "
|
|
|
|
- "Do internal reset\n", __func__);
|
|
|
|
- ASSERT(flush == 0);
|
|
|
|
- ath_reset(sc, false);
|
|
|
|
- }
|
|
|
|
|
|
+ ath_rx_requeue(sc, bf);
|
|
|
|
+ } while (1);
|
|
|
|
+
|
|
|
|
+ spin_unlock_bh(&sc->sc_rxbuflock);
|
|
|
|
|
|
return 0;
|
|
return 0;
|
|
#undef PA2DESC
|
|
#undef PA2DESC
|