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@@ -154,7 +154,7 @@ static void vx2_reset_dsp(vx_core_t *_chip)
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/* set the reset dsp bit to 0 */
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/* set the reset dsp bit to 0 */
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vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK);
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vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK);
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- snd_vx_delay(_chip, XX_DSP_RESET_WAIT_TIME);
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+ mdelay(XX_DSP_RESET_WAIT_TIME);
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chip->regCDSP |= VX_CDSP_DSP_RESET_MASK;
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chip->regCDSP |= VX_CDSP_DSP_RESET_MASK;
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/* set the reset dsp bit to 1 */
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/* set the reset dsp bit to 1 */
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@@ -362,10 +362,10 @@ static int vx2_load_xilinx_binary(vx_core_t *chip, const struct firmware *xilinx
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/* XILINX reset (wait at least 1 milisecond between reset on and off). */
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/* XILINX reset (wait at least 1 milisecond between reset on and off). */
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vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK);
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vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK);
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vx_inl(chip, CNTRL);
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vx_inl(chip, CNTRL);
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- snd_vx_delay(chip, 10);
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+ msleep(10);
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vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE);
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vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE);
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vx_inl(chip, CNTRL);
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vx_inl(chip, CNTRL);
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- snd_vx_delay(chip, 10);
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+ msleep(10);
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if (chip->type == VX_TYPE_BOARD)
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if (chip->type == VX_TYPE_BOARD)
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port = VX_CNTRL;
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port = VX_CNTRL;
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@@ -381,7 +381,7 @@ static int vx2_load_xilinx_binary(vx_core_t *chip, const struct firmware *xilinx
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}
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}
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put_xilinx_data(chip, port, 4, 0xff); /* end signature */
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put_xilinx_data(chip, port, 4, 0xff); /* end signature */
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- snd_vx_delay(chip, 200);
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+ msleep(200);
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/* test after loading (is buggy with VX222) */
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/* test after loading (is buggy with VX222) */
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if (chip->type != VX_TYPE_BOARD) {
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if (chip->type != VX_TYPE_BOARD) {
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@@ -720,17 +720,17 @@ static void vx2_reset_codec(vx_core_t *_chip)
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/* Set the reset CODEC bit to 0. */
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/* Set the reset CODEC bit to 0. */
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vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK);
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vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK);
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vx_inl(chip, CDSP);
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vx_inl(chip, CDSP);
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- snd_vx_delay(_chip, 10);
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+ msleep(10);
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/* Set the reset CODEC bit to 1. */
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/* Set the reset CODEC bit to 1. */
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chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK;
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chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK;
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vx_outl(chip, CDSP, chip->regCDSP);
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vx_outl(chip, CDSP, chip->regCDSP);
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vx_inl(chip, CDSP);
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vx_inl(chip, CDSP);
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if (_chip->type == VX_TYPE_BOARD) {
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if (_chip->type == VX_TYPE_BOARD) {
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- snd_vx_delay(_chip, 1);
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+ msleep(1);
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return;
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return;
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}
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}
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- snd_vx_delay(_chip, 5); /* additionnel wait time for AKM's */
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+ msleep(5); /* additionnel wait time for AKM's */
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vx2_write_codec_reg(_chip, AKM_CODEC_POWER_CONTROL_CMD); /* DAC power up, ADC power up, Vref power down */
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vx2_write_codec_reg(_chip, AKM_CODEC_POWER_CONTROL_CMD); /* DAC power up, ADC power up, Vref power down */
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