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@@ -298,6 +298,14 @@ nvc0_graph_takedown(struct drm_device *dev)
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nvc0_graph_destroy(dev);
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}
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+static int
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+nvc0_graph_mthd_page_flip(struct nouveau_channel *chan,
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+ u32 class, u32 mthd, u32 data)
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+{
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+ nouveau_finish_page_flip(chan, NULL);
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+ return 0;
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+}
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+
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static int
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nvc0_graph_create(struct drm_device *dev)
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{
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@@ -395,6 +403,7 @@ nvc0_graph_create(struct drm_device *dev)
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nouveau_irq_register(dev, 25, nvc0_runk140_isr);
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NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
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NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
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+ NVOBJ_MTHD (dev, 0x9039, 0x0500, nvc0_graph_mthd_page_flip);
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NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
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NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */
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return 0;
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@@ -728,9 +737,12 @@ nvc0_graph_isr(struct drm_device *dev)
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u32 class = nv_rd32(dev, 0x404200 + (subc * 4));
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if (stat & 0x00000010) {
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- NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] subc %d "
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- "class 0x%04x mthd 0x%04x data 0x%08x\n",
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- chid, inst, subc, class, mthd, data);
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+ if (nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data)) {
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+ NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] "
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+ "subc %d class 0x%04x mthd 0x%04x "
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+ "data 0x%08x\n",
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+ chid, inst, subc, class, mthd, data);
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+ }
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nv_wr32(dev, 0x400100, 0x00000010);
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stat &= ~0x00000010;
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}
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