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@@ -66,7 +66,7 @@
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#define ONEMS 0xb0 /* One Millisecond register */
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#define UTS 0xb4 /* UART Test Register */
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#endif
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-#ifdef CONFIG_ARCH_IMX
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+#if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1)
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#define BIPR1 0xb0 /* Incremental Preset Register 1 */
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#define BIPR2 0xb4 /* Incremental Preset Register 2 */
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#define BIPR3 0xb8 /* Incremental Preset Register 3 */
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@@ -96,7 +96,7 @@
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#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
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#define UCR1_SNDBRK (1<<4) /* Send break */
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#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
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-#ifdef CONFIG_ARCH_IMX
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+#if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1)
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#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
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#endif
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#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
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@@ -187,7 +187,7 @@
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#define MAX_INTERNAL_IRQ IMX_IRQS
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#endif
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-#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
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+#ifdef CONFIG_ARCH_MXC
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#define SERIAL_IMX_MAJOR 207
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#define MINOR_START 16
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#define DEV_NAME "ttymxc"
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