|
@@ -37,9 +37,9 @@ extern u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengthPciE];
|
|
|
extern u32 Rtl8192PciERadioA_Array[RadioA_ArrayLengthPciE] ;
|
|
|
#define RadioB_ArrayLengthPciE 78
|
|
|
extern u32 Rtl8192PciERadioB_Array[RadioB_ArrayLengthPciE] ;
|
|
|
-#define RadioC_ArrayLengthPciE 1
|
|
|
+#define RadioC_ArrayLengthPciE 2
|
|
|
extern u32 Rtl8192PciERadioC_Array[RadioC_ArrayLengthPciE] ;
|
|
|
-#define RadioD_ArrayLengthPciE 1
|
|
|
+#define RadioD_ArrayLengthPciE 2
|
|
|
extern u32 Rtl8192PciERadioD_Array[RadioD_ArrayLengthPciE] ;
|
|
|
#define MACPHY_ArrayLengthPciE 18
|
|
|
extern u32 Rtl8192PciEMACPHY_Array[MACPHY_ArrayLengthPciE] ;
|