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@@ -1438,17 +1438,22 @@ static void ath9k_gen_timer_start(struct ath_hw *ah,
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u32 timer_next,
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u32 timer_period)
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{
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+ struct ath_common *common = ath9k_hw_common(ah);
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+ struct ath_softc *sc = (struct ath_softc *) common->priv;
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+
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ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
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- if ((ah->ah_sc->imask & ATH9K_INT_GENTIMER) == 0) {
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+ if ((sc->imask & ATH9K_INT_GENTIMER) == 0) {
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ath9k_hw_set_interrupts(ah, 0);
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- ah->ah_sc->imask |= ATH9K_INT_GENTIMER;
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- ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
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+ sc->imask |= ATH9K_INT_GENTIMER;
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+ ath9k_hw_set_interrupts(ah, sc->imask);
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}
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}
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static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
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{
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+ struct ath_common *common = ath9k_hw_common(ah);
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+ struct ath_softc *sc = (struct ath_softc *) common->priv;
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struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
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ath9k_hw_gen_timer_stop(ah, timer);
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@@ -1456,8 +1461,8 @@ static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
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/* if no timer is enabled, turn off interrupt mask */
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if (timer_table->timer_mask.val == 0) {
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ath9k_hw_set_interrupts(ah, 0);
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- ah->ah_sc->imask &= ~ATH9K_INT_GENTIMER;
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- ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
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+ sc->imask &= ~ATH9K_INT_GENTIMER;
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+ ath9k_hw_set_interrupts(ah, sc->imask);
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}
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}
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@@ -1554,28 +1559,32 @@ static int ath_init_btcoex_timer(struct ath_softc *sc)
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static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
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{
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struct ath_hw *ah = (struct ath_hw *) hw_priv;
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+ struct ath_common *common = ath9k_hw_common(ah);
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+ struct ath_softc *sc = (struct ath_softc *) common->priv;
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if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
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unsigned long flags;
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- spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
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- iowrite32(val, ah->ah_sc->mem + reg_offset);
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- spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
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+ spin_lock_irqsave(&sc->sc_serial_rw, flags);
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+ iowrite32(val, sc->mem + reg_offset);
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+ spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
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} else
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- iowrite32(val, ah->ah_sc->mem + reg_offset);
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+ iowrite32(val, sc->mem + reg_offset);
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}
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static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
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{
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struct ath_hw *ah = (struct ath_hw *) hw_priv;
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+ struct ath_common *common = ath9k_hw_common(ah);
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+ struct ath_softc *sc = (struct ath_softc *) common->priv;
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u32 val;
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if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
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unsigned long flags;
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- spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
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- val = ioread32(ah->ah_sc->mem + reg_offset);
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- spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
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+ spin_lock_irqsave(&sc->sc_serial_rw, flags);
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+ val = ioread32(sc->mem + reg_offset);
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+ spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
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} else
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- val = ioread32(ah->ah_sc->mem + reg_offset);
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+ val = ioread32(sc->mem + reg_offset);
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return val;
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}
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@@ -1618,7 +1627,6 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
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goto bad_no_ah;
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}
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- ah->ah_sc = sc;
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ah->hw_version.devid = devid;
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ah->hw_version.subsysid = subsysid;
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sc->sc_ah = ah;
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@@ -1628,6 +1636,7 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
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common->bus_ops = bus_ops;
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common->ah = ah;
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common->hw = sc->hw;
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+ common->priv = sc;
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/*
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* Cache line size is used to size and align various
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