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@@ -718,7 +718,6 @@ static struct rgbLUT palLUT_table[] = {
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0x00}
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};
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-static void set_crt_output_path(int set_iga);
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static void dvi_patch_skew_dvp0(void);
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static void dvi_patch_skew_dvp_low(void);
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static void set_dvi_output_path(int set_iga, int output_interface);
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@@ -733,6 +732,7 @@ static void set_display_channel(void);
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static void device_off(void);
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static void device_on(void);
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static void enable_second_display_channel(void);
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+static void disable_second_display_channel(void);
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void viafb_lock_crt(void)
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{
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@@ -948,7 +948,7 @@ void viafb_set_output_path(int device, int set_iga, int output_interface)
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{
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switch (device) {
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case DEVICE_CRT:
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- set_crt_output_path(set_iga);
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+ viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
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break;
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case DEVICE_DVI:
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set_dvi_output_path(set_iga, output_interface);
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@@ -957,9 +957,6 @@ void viafb_set_output_path(int device, int set_iga, int output_interface)
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set_lcd_output_path(set_iga, output_interface);
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break;
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}
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-
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- if (set_iga == IGA2)
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- enable_second_display_channel();
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}
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static void set_source_common(u8 index, u8 offset, u8 iga)
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@@ -1030,10 +1027,22 @@ static inline void set_lvds2_source(u8 iga)
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set_source_common(0x97, 4, iga);
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}
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-static void set_crt_output_path(int set_iga)
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+void via_set_source(u32 devices, u8 iga)
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{
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- viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
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- set_crt_source(set_iga);
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+ if (devices & VIA_6C)
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+ set_6C_source(iga);
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+ if (devices & VIA_93)
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+ set_93_source(iga);
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+ if (devices & VIA_96)
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+ set_96_source(iga);
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+ if (devices & VIA_CRT)
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+ set_crt_source(iga);
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+ if (devices & VIA_DVP1)
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+ set_dvp1_source(iga);
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+ if (devices & VIA_LVDS1)
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+ set_lvds1_source(iga);
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+ if (devices & VIA_LVDS2)
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+ set_lvds2_source(iga);
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}
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static void dvi_patch_skew_dvp0(void)
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@@ -1106,8 +1115,6 @@ static void set_dvi_output_path(int set_iga, int output_interface)
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{
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switch (output_interface) {
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case INTERFACE_DVP0:
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- set_96_source(set_iga);
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- set_6C_source(set_iga);
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viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
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viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);
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viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
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@@ -1115,21 +1122,14 @@ static void set_dvi_output_path(int set_iga, int output_interface)
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break;
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case INTERFACE_DVP1:
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- if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
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- set_93_source(set_iga);
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+ if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
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viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);
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- } else {
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- set_dvp1_source(set_iga);
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- }
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viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
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break;
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case INTERFACE_DFP_HIGH:
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- if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
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+ if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
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via_write_reg_mask(VIACR, CR97, 0x03, 0x03);
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- set_lvds2_source(set_iga);
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- set_96_source(set_iga);
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- }
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viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
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break;
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@@ -1137,15 +1137,9 @@ static void set_dvi_output_path(int set_iga, int output_interface)
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case INTERFACE_DFP_LOW:
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if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
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break;
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- set_dvp1_source(set_iga);
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- set_lvds1_source(set_iga);
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viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
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dvi_patch_skew_dvp_low();
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break;
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-
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- case INTERFACE_TMDS:
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- set_lvds1_source(set_iga);
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- break;
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}
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if (set_iga == IGA2) {
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@@ -1163,53 +1157,19 @@ static void set_lcd_output_path(int set_iga, int output_interface)
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viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
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viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
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switch (output_interface) {
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- case INTERFACE_DVP0:
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- set_96_source(set_iga);
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- if (set_iga == IGA2)
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- viafb_write_reg(CR91, VIACR, 0x00);
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- break;
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-
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- case INTERFACE_DVP1:
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- set_dvp1_source(set_iga);
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- if (set_iga == IGA2)
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- viafb_write_reg(CR91, VIACR, 0x00);
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- break;
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-
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- case INTERFACE_DFP_HIGH:
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- set_lvds2_source(set_iga);
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- set_96_source(set_iga);
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- if (set_iga == IGA2)
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- viafb_write_reg(CR91, VIACR, 0x00);
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- break;
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-
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- case INTERFACE_DFP_LOW:
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- set_lvds1_source(set_iga);
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- set_dvp1_source(set_iga);
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- if (set_iga == IGA2)
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- viafb_write_reg(CR91, VIACR, 0x00);
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- break;
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-
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case INTERFACE_DFP:
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if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
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|| (UNICHROME_P4M890 ==
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viaparinfo->chip_info->gfx_chip_name))
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viafb_write_reg_mask(CR97, VIACR, 0x84,
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BIT7 + BIT2 + BIT1 + BIT0);
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-
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- set_lvds1_source(set_iga);
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- set_lvds2_source(set_iga);
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+ case INTERFACE_DVP0:
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+ case INTERFACE_DVP1:
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+ case INTERFACE_DFP_HIGH:
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+ case INTERFACE_DFP_LOW:
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if (set_iga == IGA2)
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viafb_write_reg(CR91, VIACR, 0x00);
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break;
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-
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- case INTERFACE_LVDS0:
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- case INTERFACE_LVDS0LVDS1:
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- set_lvds1_source(set_iga);
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- break;
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-
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- case INTERFACE_LVDS1:
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- set_lvds2_source(set_iga);
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- break;
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}
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}
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@@ -2454,6 +2414,13 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
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via_set_primary_color_depth(viaparinfo->depth);
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via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
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: viaparinfo->depth);
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+ via_set_source(viaparinfo->shared->iga1_devices, IGA1);
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+ via_set_source(viaparinfo->shared->iga2_devices, IGA2);
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+ if (viaparinfo->shared->iga2_devices)
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+ enable_second_display_channel();
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+ else
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+ disable_second_display_channel();
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+
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/* Update Refresh Rate Setting */
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/* Clear On Screen */
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@@ -2647,6 +2614,14 @@ static void enable_second_display_channel(void)
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viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
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}
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+static void disable_second_display_channel(void)
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+{
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+ /* to disable second display channel. */
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+ viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
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+ viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
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+ viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
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+}
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+
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void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
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*p_gfx_dpa_setting)
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{
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