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@@ -141,8 +141,7 @@ int r600_pcie_gart_enable(struct radeon_device *rdev)
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r = radeon_gart_table_vram_pin(rdev);
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if (r)
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return r;
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- for (i = 0; i < rdev->gart.num_gpu_pages; i++)
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- r600_gart_clear_page(rdev, i);
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+
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/* Setup L2 cache */
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WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
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ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
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@@ -1477,6 +1476,14 @@ int r600_resume(struct radeon_device *rdev)
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if (r)
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return r;
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r600_gpu_init(rdev);
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+
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+ r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
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+ &rdev->r600_blit.shader_gpu_addr);
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+ if (r) {
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+ DRM_ERROR("failed to pin blit object %d\n", r);
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+ return r;
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+ }
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+
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r = radeon_ring_init(rdev, rdev->cp.ring_size);
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if (r)
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return r;
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@@ -1496,7 +1503,11 @@ int r600_suspend(struct radeon_device *rdev)
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{
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/* FIXME: we should wait for ring to be empty */
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r600_cp_stop(rdev);
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+ rdev->cp.ready = false;
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+
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r600_pcie_gart_disable(rdev);
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+ /* unpin shaders bo */
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+ radeon_object_unpin(rdev->r600_blit.shader_obj);
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return 0;
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}
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@@ -1579,6 +1590,12 @@ int r600_init(struct radeon_device *rdev)
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return r;
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rdev->accel_working = true;
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+ r = r600_blit_init(rdev);
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+ if (r) {
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+ DRM_ERROR("radeon: failled blitter (%d).\n", r);
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+ return r;
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+ }
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+
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r = r600_resume(rdev);
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if (r) {
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if (rdev->flags & RADEON_IS_AGP) {
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@@ -1595,11 +1612,6 @@ int r600_init(struct radeon_device *rdev)
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DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
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rdev->accel_working = false;
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}
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- r = r600_blit_init(rdev);
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- if (r) {
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- DRM_ERROR("radeon: failled blitter (%d).\n", r);
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- rdev->accel_working = false;
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- }
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r = radeon_ib_test(rdev);
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if (r) {
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DRM_ERROR("radeon: failled testing IB (%d).\n", r);
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