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@@ -149,8 +149,7 @@ static void nvGetClocks(struct nvidia_par *par, unsigned int *MClk,
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pll = NV_RD32(par->PMC, 0x4024);
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M = pll & 0xFF;
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N = (pll >> 8) & 0xFF;
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- if (((par->Chipset & 0xfff0) == 0x0290) ||
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- ((par->Chipset & 0xfff0) == 0x0390)) {
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+ if (((par->Chipset & 0xfff0) == 0x0290) || ((par->Chipset & 0xfff0) == 0x0390) || ((par->Chipset & 0xfff0) == 0x02E0)) {
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MB = 1;
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NB = 1;
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} else {
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@@ -963,6 +962,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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if (((par->Chipset & 0xfff0) == 0x0090) ||
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((par->Chipset & 0xfff0) == 0x01D0) ||
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+ ((par->Chipset & 0xfff0) == 0x02E0) ||
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((par->Chipset & 0xfff0) == 0x0290))
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regions = 15;
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for(i = 0; i < regions; i++) {
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@@ -1275,6 +1275,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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0x00100000);
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break;
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case 0x0090:
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+ case 0x02E0:
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case 0x0290:
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NV_WR32(par->PRAMDAC, 0x0608,
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NV_RD32(par->PRAMDAC, 0x0608) |
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@@ -1352,6 +1353,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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} else {
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if (((par->Chipset & 0xfff0) == 0x0090) ||
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((par->Chipset & 0xfff0) == 0x01D0) ||
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+ ((par->Chipset & 0xfff0) == 0x02E0) ||
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((par->Chipset & 0xfff0) == 0x0290)) {
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for (i = 0; i < 60; i++) {
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NV_WR32(par->PGRAPH,
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@@ -1403,6 +1405,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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} else {
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if ((par->Chipset & 0xfff0) == 0x0090 ||
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(par->Chipset & 0xfff0) == 0x01D0 ||
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+ (par->Chipset & 0xfff0) == 0x02E0 ||
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(par->Chipset & 0xfff0) == 0x0290) {
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NV_WR32(par->PGRAPH, 0x0DF0,
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NV_RD32(par->PFB, 0x0200));
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