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@@ -187,16 +187,20 @@ int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
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if (!saif)
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return -EINVAL;
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+ /* Clear Reset */
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+ __raw_writel(BM_SAIF_CTRL_SFTRST,
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+ saif->base + SAIF_CTRL + MXS_CLR_ADDR);
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+
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+ /* FIXME: need clear clk gate for register r/w */
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+ __raw_writel(BM_SAIF_CTRL_CLKGATE,
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+ saif->base + SAIF_CTRL + MXS_CLR_ADDR);
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+
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stat = __raw_readl(saif->base + SAIF_STAT);
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if (stat & BM_SAIF_STAT_BUSY) {
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dev_err(saif->dev, "error: busy\n");
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return -EBUSY;
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}
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- /* Clear Reset */
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- __raw_writel(BM_SAIF_CTRL_SFTRST,
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- saif->base + SAIF_CTRL + MXS_CLR_ADDR);
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-
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saif->mclk_in_use = 1;
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ret = mxs_saif_set_clk(saif, mclk, rate);
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if (ret)
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@@ -207,8 +211,6 @@ int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
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return ret;
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/* enable MCLK output */
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- __raw_writel(BM_SAIF_CTRL_CLKGATE,
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- saif->base + SAIF_CTRL + MXS_CLR_ADDR);
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__raw_writel(BM_SAIF_CTRL_RUN,
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saif->base + SAIF_CTRL + MXS_SET_ADDR);
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@@ -303,6 +305,10 @@ static int mxs_saif_startup(struct snd_pcm_substream *substream,
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__raw_writel(BM_SAIF_CTRL_SFTRST,
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saif->base + SAIF_CTRL + MXS_CLR_ADDR);
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+ /* clear clock gate */
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+ __raw_writel(BM_SAIF_CTRL_CLKGATE,
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+ saif->base + SAIF_CTRL + MXS_CLR_ADDR);
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+
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return 0;
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}
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@@ -379,10 +385,6 @@ static int mxs_saif_prepare(struct snd_pcm_substream *substream,
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{
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struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
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- /* clear clock gate */
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- __raw_writel(BM_SAIF_CTRL_CLKGATE,
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- saif->base + SAIF_CTRL + MXS_CLR_ADDR);
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-
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/* enable FIFO error irqs */
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__raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
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saif->base + SAIF_CTRL + MXS_SET_ADDR);
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