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@@ -497,21 +497,20 @@ static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
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unsigned long flags;
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spin_lock_irqsave(&tp->indirect_lock, flags);
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- pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
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- pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
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+ if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
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+ pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
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+ pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
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- /* Always leave this as zero. */
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- pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
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- spin_unlock_irqrestore(&tp->indirect_lock, flags);
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-}
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+ /* Always leave this as zero. */
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+ pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
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+ } else {
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+ tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
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+ tw32_f(TG3PCI_MEM_WIN_DATA, val);
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-static void tg3_write_mem_fast(struct tg3 *tp, u32 off, u32 val)
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-{
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- /* If no workaround is needed, write to mem space directly */
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- if (tp->write32 != tg3_write_indirect_reg32)
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- tw32(NIC_SRAM_WIN_BASE + off, val);
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- else
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- tg3_write_mem(tp, off, val);
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+ /* Always leave this as zero. */
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+ tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
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+ }
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+ spin_unlock_irqrestore(&tp->indirect_lock, flags);
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}
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static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
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@@ -519,11 +518,19 @@ static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
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unsigned long flags;
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spin_lock_irqsave(&tp->indirect_lock, flags);
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- pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
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- pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
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+ if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
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+ pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
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+ pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
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- /* Always leave this as zero. */
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- pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
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+ /* Always leave this as zero. */
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+ pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
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+ } else {
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+ tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
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+ *val = tr32(TG3PCI_MEM_WIN_DATA);
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+
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+ /* Always leave this as zero. */
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+ tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
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+ }
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spin_unlock_irqrestore(&tp->indirect_lock, flags);
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}
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@@ -1367,12 +1374,12 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
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}
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}
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+ tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
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+
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/* Finally, set the new power state. */
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pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
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udelay(100); /* Delay after power state change */
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- tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
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-
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return 0;
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}
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@@ -6539,11 +6546,11 @@ static void tg3_timer(unsigned long __opaque)
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if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
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u32 val;
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- tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_MBOX,
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- FWCMD_NICDRV_ALIVE2);
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- tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
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+ tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
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+ FWCMD_NICDRV_ALIVE2);
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+ tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
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/* 5 seconds timeout */
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- tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
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+ tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
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val = tr32(GRC_RX_CPU_EVENT);
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val |= (1 << 14);
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tw32(GRC_RX_CPU_EVENT, val);
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@@ -9539,8 +9546,11 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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tp->led_ctrl = LED_CTRL_MODE_PHY_1;
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/* Do not even try poking around in here on Sun parts. */
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- if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
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+ if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
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+ /* All SUN chips are built-in LOMs. */
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+ tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
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return;
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+ }
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tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
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if (val == NIC_SRAM_DATA_SIG_MAGIC) {
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@@ -9638,9 +9648,7 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
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tp->led_ctrl = LED_CTRL_MODE_PHY_2;
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- if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
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- (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
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- (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
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+ if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)
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tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
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if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
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@@ -10265,6 +10273,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
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}
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+ if (tp->write32 == tg3_write_indirect_reg32 ||
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+ ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
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+ (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
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+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) ||
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+ (tp->tg3_flags2 & TG3_FLG2_SUN_570X))
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+ tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
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+
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/* Get eeprom hw config before calling tg3_set_power_state().
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* In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
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* determined before calling tg3_set_power_state() so that
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