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@@ -146,9 +146,11 @@ int cx88_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
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fields++;
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fields++;
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/* estimate risc mem: worst case is one write per page border +
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/* estimate risc mem: worst case is one write per page border +
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- one write per scan line + syncs + jump (all 2 dwords) */
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- instructions = (bpl * lines * fields) / PAGE_SIZE + lines * fields;
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- instructions += 3 + 4;
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+ one write per scan line + syncs + jump (all 2 dwords). Padding
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+ can cause next bpl to start close to a page border. First DMA
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+ region may be smaller than PAGE_SIZE */
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+ instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
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+ instructions += 2;
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if ((rc = btcx_riscmem_alloc(pci,risc,instructions*8)) < 0)
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if ((rc = btcx_riscmem_alloc(pci,risc,instructions*8)) < 0)
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return rc;
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return rc;
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@@ -176,9 +178,11 @@ int cx88_risc_databuffer(struct pci_dev *pci, struct btcx_riscmem *risc,
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int rc;
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int rc;
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/* estimate risc mem: worst case is one write per page border +
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/* estimate risc mem: worst case is one write per page border +
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- one write per scan line + syncs + jump (all 2 dwords) */
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- instructions = (bpl * lines) / PAGE_SIZE + lines;
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- instructions += 3 + 4;
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+ one write per scan line + syncs + jump (all 2 dwords). Here
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+ there is no padding and no sync. First DMA region may be smaller
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+ than PAGE_SIZE */
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+ instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
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+ instructions += 1;
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if ((rc = btcx_riscmem_alloc(pci,risc,instructions*8)) < 0)
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if ((rc = btcx_riscmem_alloc(pci,risc,instructions*8)) < 0)
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return rc;
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return rc;
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