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@@ -8184,8 +8184,8 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
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I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
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I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
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if (intel_enable_rc6(dev_priv->dev))
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if (intel_enable_rc6(dev_priv->dev))
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- rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
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- GEN6_RC_CTL_RC6_ENABLE;
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+ rc6_mask = GEN6_RC_CTL_RC6_ENABLE |
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+ (IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0;
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I915_WRITE(GEN6_RC_CONTROL,
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I915_WRITE(GEN6_RC_CONTROL,
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rc6_mask |
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rc6_mask |
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@@ -8463,12 +8463,32 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
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I915_WRITE(WM2_LP_ILK, 0);
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I915_WRITE(WM2_LP_ILK, 0);
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I915_WRITE(WM1_LP_ILK, 0);
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I915_WRITE(WM1_LP_ILK, 0);
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+ /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
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+ * This implements the WaDisableRCZUnitClockGating workaround.
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+ */
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+ I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
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+
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I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
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I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
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I915_WRITE(IVB_CHICKEN3,
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I915_WRITE(IVB_CHICKEN3,
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CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
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CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
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CHICKEN3_DGMG_DONE_FIX_DISABLE);
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CHICKEN3_DGMG_DONE_FIX_DISABLE);
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+ /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
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+ I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
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+ GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
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+
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+ /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
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+ I915_WRITE(GEN7_L3CNTLREG1,
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+ GEN7_WA_FOR_GEN7_L3_CONTROL);
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+ I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
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+ GEN7_WA_L3_CHICKEN_MODE);
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+
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+ /* This is required by WaCatErrorRejectionIssue */
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+ I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
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+ I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
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+ GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
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+
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for_each_pipe(pipe) {
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for_each_pipe(pipe) {
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I915_WRITE(DSPCNTR(pipe),
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I915_WRITE(DSPCNTR(pipe),
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I915_READ(DSPCNTR(pipe)) |
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I915_READ(DSPCNTR(pipe)) |
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