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@@ -19,6 +19,47 @@
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#include <mach/cp_intc.h>
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#include <mach/da8xx.h>
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+#include <mach/mux.h>
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+
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+#define HAWKBOARD_PHY_ID "0:07"
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+
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+static short omapl138_hawk_mii_pins[] __initdata = {
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+ DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
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+ DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
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+ DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
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+ DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
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+ DA850_MDIO_D,
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+ -1
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+};
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+
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+static __init void omapl138_hawk_config_emac(void)
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+{
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+ void __iomem *cfgchip3 = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
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+ int ret;
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+ u32 val;
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+ struct davinci_soc_info *soc_info = &davinci_soc_info;
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+
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+ val = __raw_readl(cfgchip3);
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+ val &= ~BIT(8);
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+ ret = davinci_cfg_reg_list(omapl138_hawk_mii_pins);
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+ if (ret) {
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+ pr_warning("%s: cpgmac/mii mux setup failed: %d\n",
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+ __func__, ret);
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+ return;
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+ }
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+
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+ /* configure the CFGCHIP3 register for MII */
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+ __raw_writel(val, cfgchip3);
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+ pr_info("EMAC: MII PHY configured\n");
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+
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+ soc_info->emac_pdata->phy_id = HAWKBOARD_PHY_ID;
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+
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+ ret = da8xx_register_emac();
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+ if (ret)
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+ pr_warning("%s: emac registration failed: %d\n",
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+ __func__, ret);
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+}
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+
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static struct davinci_uart_config omapl138_hawk_uart_config __initdata = {
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.enabled_uarts = 0x7,
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@@ -30,6 +71,8 @@ static __init void omapl138_hawk_init(void)
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davinci_serial_init(&omapl138_hawk_uart_config);
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+ omapl138_hawk_config_emac();
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+
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ret = da8xx_register_watchdog();
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if (ret)
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pr_warning("omapl138_hawk_init: "
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