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@@ -1313,14 +1313,18 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
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if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
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radeon_wait_for_vblank(rdev, i);
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tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
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WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
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}
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} else {
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tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
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if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
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radeon_wait_for_vblank(rdev, i);
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tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
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WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
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}
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}
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/* wait for the next frame */
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@@ -1378,11 +1382,15 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
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if (ASIC_IS_DCE6(rdev)) {
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tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
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tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
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WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
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} else {
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tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
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tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
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WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
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+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
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}
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/* wait for the next frame */
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frame_count = radeon_get_vblank_counter(rdev, i);
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