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@@ -75,6 +75,23 @@ MODULE_LICENSE("GPL");
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rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
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H2M_MAILBOX_CSR_OWNER, (__reg))
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+static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
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+{
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+ /* check for rt2872 on SoC */
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+ if (!rt2x00_is_soc(rt2x00dev) ||
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+ !rt2x00_rt(rt2x00dev, RT2872))
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+ return false;
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+
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+ /* we know for sure that these rf chipsets are used on rt305x boards */
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+ if (rt2x00_rf(rt2x00dev, RF3020) ||
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+ rt2x00_rf(rt2x00dev, RF3021) ||
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+ rt2x00_rf(rt2x00dev, RF3022))
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+ return true;
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+
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+ NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
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+ return false;
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+}
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+
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static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
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const unsigned int word, const u8 value)
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{
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@@ -1555,6 +1572,9 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
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rt2800_wait_bbp_ready(rt2x00dev)))
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return -EACCES;
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+ if (rt2800_is_305x_soc(rt2x00dev))
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+ rt2800_bbp_write(rt2x00dev, 31, 0x08);
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+
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rt2800_bbp_write(rt2x00dev, 65, 0x2c);
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rt2800_bbp_write(rt2x00dev, 66, 0x38);
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@@ -1575,6 +1595,9 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
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rt2800_bbp_write(rt2x00dev, 79, 0x13);
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rt2800_bbp_write(rt2x00dev, 80, 0x05);
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rt2800_bbp_write(rt2x00dev, 81, 0x33);
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+ } else if (rt2800_is_305x_soc(rt2x00dev)) {
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+ rt2800_bbp_write(rt2x00dev, 78, 0x0e);
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+ rt2800_bbp_write(rt2x00dev, 80, 0x08);
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} else {
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rt2800_bbp_write(rt2x00dev, 81, 0x37);
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}
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@@ -1595,12 +1618,16 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
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if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
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rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
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rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
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- rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
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+ rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
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+ rt2800_is_305x_soc(rt2x00dev))
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rt2800_bbp_write(rt2x00dev, 103, 0xc0);
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else
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rt2800_bbp_write(rt2x00dev, 103, 0x00);
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- rt2800_bbp_write(rt2x00dev, 105, 0x05);
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+ if (rt2800_is_305x_soc(rt2x00dev))
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+ rt2800_bbp_write(rt2x00dev, 105, 0x01);
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+ else
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+ rt2800_bbp_write(rt2x00dev, 105, 0x05);
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rt2800_bbp_write(rt2x00dev, 106, 0x35);
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if (rt2x00_rt(rt2x00dev, RT3071) ||
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@@ -1617,11 +1644,6 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
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rt2800_bbp_write(rt2x00dev, 138, value);
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}
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- if (rt2x00_rt(rt2x00dev, RT2872)) {
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- rt2800_bbp_write(rt2x00dev, 31, 0x08);
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- rt2800_bbp_write(rt2x00dev, 78, 0x0e);
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- rt2800_bbp_write(rt2x00dev, 80, 0x08);
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- }
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for (i = 0; i < EEPROM_BBP_SIZE; i++) {
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rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
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@@ -1708,7 +1730,7 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
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!rt2x00_rt(rt2x00dev, RT3071) &&
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!rt2x00_rt(rt2x00dev, RT3090) &&
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!rt2x00_rt(rt2x00dev, RT3390) &&
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- !(rt2x00_is_soc(rt2x00dev) && rt2x00_rt(rt2x00dev, RT2872)))
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+ !rt2800_is_305x_soc(rt2x00dev))
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return 0;
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/*
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@@ -1776,7 +1798,7 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
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rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
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rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
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rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
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- } else if (rt2x00_rt(rt2x00dev, RT2872)) {
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+ } else if (rt2800_is_305x_soc(rt2x00dev)) {
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rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
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rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
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rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
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@@ -1807,6 +1829,9 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
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rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
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rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
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rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
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+ rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
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+ rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
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+ return 0;
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}
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if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
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