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@@ -56,6 +56,9 @@
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#define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
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#define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
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+/* Used for Spansion flashes only. */
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+#define OPCODE_BRWR 0x17 /* Bank register write */
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+
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/* Status Register bits. */
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#define SR_WIP 1 /* Write in progress */
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#define SR_WEL 2 /* Write enable latch */
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@@ -161,11 +164,18 @@ static inline int write_disable(struct m25p *flash)
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/*
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* Enable/disable 4-byte addressing mode.
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*/
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-static inline int set_4byte(struct m25p *flash, int enable)
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+static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
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{
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- u8 code = enable ? OPCODE_EN4B : OPCODE_EX4B;
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-
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- return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
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+ switch (JEDEC_MFR(jedec_id)) {
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+ case CFI_MFR_MACRONIX:
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+ flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
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+ return spi_write(flash->spi, flash->command, 1);
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+ default:
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+ /* Spansion style */
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+ flash->command[0] = OPCODE_BRWR;
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+ flash->command[1] = enable << 7;
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+ return spi_write(flash->spi, flash->command, 2);
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+ }
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}
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/*
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@@ -688,6 +698,8 @@ static const struct spi_device_id m25p_ids[] = {
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{ "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
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{ "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SECT_4K) },
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{ "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
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+ { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
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+ { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 0) },
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{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
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{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
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{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
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@@ -921,7 +933,7 @@ static int __devinit m25p_probe(struct spi_device *spi)
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/* enable 4-byte addressing if the device exceeds 16MiB */
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if (flash->mtd.size > 0x1000000) {
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flash->addr_width = 4;
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- set_4byte(flash, 1);
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+ set_4byte(flash, info->jedec_id, 1);
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} else
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flash->addr_width = 3;
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}
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