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@@ -43,6 +43,7 @@
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struct omap_mcbsp_data {
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unsigned int bus_id;
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struct omap_mcbsp_reg_cfg regs;
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+ unsigned int fmt;
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/*
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* Flags indicating is the bus already activated and configured by
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* another substream
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@@ -200,6 +201,7 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
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struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
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struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
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int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
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+ int wlen;
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unsigned long port;
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if (cpu_class_is_omap1()) {
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@@ -244,19 +246,29 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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/* Set word lengths */
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+ wlen = 16;
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regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
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regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
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regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
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regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
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- /* Set FS period and length in terms of bit clock periods */
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- regs->srgr2 |= FPER(16 * 2 - 1);
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- regs->srgr1 |= FWID(16 - 1);
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break;
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default:
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/* Unsupported PCM format */
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return -EINVAL;
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}
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+ /* Set FS period and length in terms of bit clock periods */
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+ switch (mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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+ case SND_SOC_DAIFMT_I2S:
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+ regs->srgr2 |= FPER(wlen * 2 - 1);
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+ regs->srgr1 |= FWID(wlen - 1);
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+ break;
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+ case SND_SOC_DAIFMT_DSP_A:
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+ regs->srgr2 |= FPER(wlen * 2 - 1);
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+ regs->srgr1 |= FWID(0);
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+ break;
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+ }
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+
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omap_mcbsp_config(bus_id, &mcbsp_data->regs);
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mcbsp_data->configured = 1;
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@@ -272,10 +284,12 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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{
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struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
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struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
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+ unsigned int temp_fmt = fmt;
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if (mcbsp_data->configured)
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return 0;
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+ mcbsp_data->fmt = fmt;
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memset(regs, 0, sizeof(*regs));
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/* Generic McBSP register settings */
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regs->spcr2 |= XINTM(3) | FREE;
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@@ -293,6 +307,8 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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/* 0-bit data delay */
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regs->rcr2 |= RDATDLY(0);
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regs->xcr2 |= XDATDLY(0);
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+ /* Invert bit clock and FS polarity configuration for DSP_A */
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+ temp_fmt ^= SND_SOC_DAIFMT_IB_IF;
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break;
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default:
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/* Unsupported data format */
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@@ -316,7 +332,7 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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}
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/* Set bit clock (CLKX/CLKR) and FS polarities */
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- switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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+ switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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/*
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* Normal BCLK + FS.
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