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@@ -467,6 +467,49 @@ static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
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}
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}
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+#if 0
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+//done but not used yet
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+static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
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+{
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+ const u16 mdio_control = 0x128;
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+ const u16 mdio_data = 0x12C;
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+ int max_retries = 10;
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+ u16 ret = 0;
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+ u32 v;
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+ int i;
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+
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+ v = 0x80; /* Enable Preamble Sequence */
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+ v |= 0x2; /* MDIO Clock Divisor */
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+ pcicore_write32(pc, mdio_control, v);
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+
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+ if (pc->dev->id.revision >= 10) {
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+ max_retries = 200;
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+ ssb_pcie_mdio_set_phy(pc, device);
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+ }
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+
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+ v = (1 << 30); /* Start of Transaction */
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+ v |= (1 << 29); /* Read Transaction */
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+ v |= (1 << 17); /* Turnaround */
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+ if (pc->dev->id.revision < 10)
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+ v |= (u32)device << 22;
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+ v |= (u32)address << 18;
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+ pcicore_write32(pc, mdio_data, v);
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+ /* Wait for the device to complete the transaction */
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+ udelay(10);
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+ for (i = 0; i < 200; i++) {
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+ v = pcicore_read32(pc, mdio_control);
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+ if (v & 0x100 /* Trans complete */) {
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+ udelay(10);
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+ ret = pcicore_read32(pc, mdio_data);
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+ break;
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+ }
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+ msleep(1);
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+ }
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+ pcicore_write32(pc, mdio_control, 0);
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+ return ret;
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+}
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+#endif
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+
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static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
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u8 address, u16 data)
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{
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