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@@ -31,7 +31,8 @@
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#define DRV_VERSION "0.3"
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enum {
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- MMIO_BAR = 5,
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+ MMIO_BAR_PCI = 5,
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+ MMIO_BAR_CARDBUS = 1,
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NR_PORTS = 2,
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@@ -197,6 +198,7 @@ struct inic_pkt {
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} __packed;
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struct inic_host_priv {
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+ void __iomem *mmio_base;
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u16 cached_hctl;
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};
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@@ -221,7 +223,9 @@ static const int scr_map[] = {
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static void __iomem *inic_port_base(struct ata_port *ap)
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{
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- return ap->host->iomap[MMIO_BAR] + ap->port_no * PORT_SIZE;
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+ struct inic_host_priv *hpriv = ap->host->private_data;
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+
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+ return hpriv->mmio_base + ap->port_no * PORT_SIZE;
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}
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static void inic_reset_port(void __iomem *port_base)
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@@ -378,11 +382,11 @@ static void inic_host_intr(struct ata_port *ap)
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static irqreturn_t inic_interrupt(int irq, void *dev_instance)
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{
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struct ata_host *host = dev_instance;
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- void __iomem *mmio_base = host->iomap[MMIO_BAR];
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+ struct inic_host_priv *hpriv = host->private_data;
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u16 host_irq_stat;
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int i, handled = 0;;
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- host_irq_stat = readw(mmio_base + HOST_IRQ_STAT);
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+ host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT);
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if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
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goto out;
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@@ -770,7 +774,6 @@ static int inic_pci_device_resume(struct pci_dev *pdev)
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{
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struct ata_host *host = dev_get_drvdata(&pdev->dev);
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struct inic_host_priv *hpriv = host->private_data;
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- void __iomem *mmio_base = host->iomap[MMIO_BAR];
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int rc;
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rc = ata_pci_device_do_resume(pdev);
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@@ -778,7 +781,7 @@ static int inic_pci_device_resume(struct pci_dev *pdev)
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return rc;
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if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
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- rc = init_controller(mmio_base, hpriv->cached_hctl);
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+ rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
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if (rc)
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return rc;
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}
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@@ -796,6 +799,7 @@ static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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struct ata_host *host;
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struct inic_host_priv *hpriv;
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void __iomem * const *iomap;
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+ int mmio_bar;
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int i, rc;
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if (!printed_version++)
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@@ -809,22 +813,30 @@ static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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host->private_data = hpriv;
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- /* acquire resources and fill host */
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+ /* Acquire resources and fill host. Note that PCI and cardbus
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+ * use different BARs.
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+ */
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rc = pcim_enable_device(pdev);
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if (rc)
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return rc;
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- rc = pcim_iomap_regions(pdev, 1 << MMIO_BAR, DRV_NAME);
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+ if (pci_resource_flags(pdev, MMIO_BAR_PCI) & IORESOURCE_MEM)
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+ mmio_bar = MMIO_BAR_PCI;
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+ else
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+ mmio_bar = MMIO_BAR_CARDBUS;
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+
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+ rc = pcim_iomap_regions(pdev, 1 << mmio_bar, DRV_NAME);
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if (rc)
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return rc;
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host->iomap = iomap = pcim_iomap_table(pdev);
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- hpriv->cached_hctl = readw(iomap[MMIO_BAR] + HOST_CTL);
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+ hpriv->mmio_base = iomap[mmio_bar];
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+ hpriv->cached_hctl = readw(hpriv->mmio_base + HOST_CTL);
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for (i = 0; i < NR_PORTS; i++) {
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struct ata_port *ap = host->ports[i];
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- ata_port_pbar_desc(ap, MMIO_BAR, -1, "mmio");
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- ata_port_pbar_desc(ap, MMIO_BAR, i * PORT_SIZE, "port");
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+ ata_port_pbar_desc(ap, mmio_bar, -1, "mmio");
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+ ata_port_pbar_desc(ap, mmio_bar, i * PORT_SIZE, "port");
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}
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/* Set dma_mask. This devices doesn't support 64bit addressing. */
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@@ -854,7 +866,7 @@ static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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return rc;
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}
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- rc = init_controller(iomap[MMIO_BAR], hpriv->cached_hctl);
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+ rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
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if (rc) {
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dev_printk(KERN_ERR, &pdev->dev,
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"failed to initialize controller\n");
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