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@@ -2358,26 +2358,20 @@ void omap_dma_global_context_save(void)
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void omap_dma_global_context_restore(void)
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{
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- dma_write(0x2, OCP_SYSCONFIG);
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- while (!__raw_readl(omap_dma_base + OMAP_DMA4_SYSSTATUS))
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- ;
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dma_write(omap_dma_global_context.dma_gcr, GCR);
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dma_write(omap_dma_global_context.dma_ocp_sysconfig,
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OCP_SYSCONFIG);
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dma_write(omap_dma_global_context.dma_irqenable_l0,
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IRQENABLE_L0);
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-}
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-
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-void omap_dma_disable_irq(int lch)
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-{
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- u32 val;
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- if (cpu_class_is_omap2()) {
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- /* Disable interrupts */
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- val = dma_read(IRQENABLE_L0);
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- val &= ~(1 << lch);
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- dma_write(val, IRQENABLE_L0);
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- }
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+ /*
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+ * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
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+ * after secure sram context save and restore. Hence we need to
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+ * manually clear those IRQs to avoid spurious interrupts. This
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+ * affects only secure devices.
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+ */
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+ if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
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+ dma_write(0x3 , IRQSTATUS_L0);
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}
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/*----------------------------------------------------------------------------*/
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@@ -2515,8 +2509,8 @@ static int __init omap_init_dma(void)
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setup_irq(irq, &omap24xx_dma_irq);
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}
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- /* Enable smartidle idlemodes and autoidle */
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if (cpu_is_omap34xx()) {
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+ /* Enable smartidle idlemodes and autoidle */
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u32 v = dma_read(OCP_SYSCONFIG);
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v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
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DMA_SYSCONFIG_SIDLEMODE_MASK |
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@@ -2525,6 +2519,13 @@ static int __init omap_init_dma(void)
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DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
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DMA_SYSCONFIG_AUTOIDLE);
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dma_write(v , OCP_SYSCONFIG);
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+ /* reserve dma channels 0 and 1 in high security devices */
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+ if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
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+ printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
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+ "HS ROM code\n");
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+ dma_chan[0].dev_id = 0;
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+ dma_chan[1].dev_id = 1;
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+ }
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}
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