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@@ -431,31 +431,6 @@ enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
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}
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}
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-/* calculate clock rates using dividers in cinfo */
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-int dss_calc_clock_rates(struct dss_clock_info *cinfo)
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-{
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- if (dss.dpll4_m4_ck) {
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- unsigned long prate;
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- u16 fck_div_max = 16;
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-
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- if (cpu_is_omap3630() || cpu_is_omap44xx())
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- fck_div_max = 32;
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-
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- if (cinfo->fck_div > fck_div_max || cinfo->fck_div == 0)
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- return -EINVAL;
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-
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- prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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-
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- cinfo->fck = prate / cinfo->fck_div;
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- } else {
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- if (cinfo->fck_div != 0)
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- return -EINVAL;
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- cinfo->fck = clk_get_rate(dss.dss_clk);
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- }
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-
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- return 0;
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-}
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-
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int dss_set_clock_div(struct dss_clock_info *cinfo)
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{
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if (dss.dpll4_m4_ck) {
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@@ -478,26 +453,6 @@ int dss_set_clock_div(struct dss_clock_info *cinfo)
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return 0;
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}
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-int dss_get_clock_div(struct dss_clock_info *cinfo)
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-{
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- cinfo->fck = clk_get_rate(dss.dss_clk);
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-
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- if (dss.dpll4_m4_ck) {
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- unsigned long prate;
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-
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- prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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-
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- if (cpu_is_omap3630() || cpu_is_omap44xx())
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- cinfo->fck_div = prate / (cinfo->fck);
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- else
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- cinfo->fck_div = prate / (cinfo->fck / 2);
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- } else {
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- cinfo->fck_div = 0;
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- }
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-
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- return 0;
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-}
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-
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unsigned long dss_get_dpll4_rate(void)
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{
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if (dss.dpll4_m4_ck)
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