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@@ -51,12 +51,18 @@
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#define AUTCPU12_SMC_BASE (CS1_PHYS_BASE + 0x06000000)
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#define AUTCPU12_SMC_SEL_BASE (AUTCPU12_SMC_BASE + 0x10)
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+/* NAND flash */
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#define AUTCPU12_MMGPIO_BASE (CLPS711X_NR_GPIO)
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#define AUTCPU12_SMC_NCE (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
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#define AUTCPU12_SMC_RDY CLPS711X_GPIO(1, 2)
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#define AUTCPU12_SMC_ALE CLPS711X_GPIO(1, 3)
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#define AUTCPU12_SMC_CLE CLPS711X_GPIO(1, 3)
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+/* LCD contrast digital potentiometer */
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+#define AUTCPU12_DPOT_CS CLPS711X_GPIO(4, 0)
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+#define AUTCPU12_DPOT_CLK CLPS711X_GPIO(4, 1)
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+#define AUTCPU12_DPOT_UD CLPS711X_GPIO(4, 2)
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+
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static struct resource autcpu12_cs8900_resource[] __initdata = {
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DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K),
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DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ),
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@@ -148,6 +154,12 @@ static struct platform_device autcpu12_mmgpio_pdev __initdata = {
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},
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};
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+static const struct gpio autcpu12_gpios[] __initconst = {
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+ { AUTCPU12_DPOT_CS, GPIOF_OUT_INIT_HIGH, "DPOT CS" },
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+ { AUTCPU12_DPOT_CLK, GPIOF_OUT_INIT_LOW, "DPOT CLK" },
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+ { AUTCPU12_DPOT_UD, GPIOF_OUT_INIT_LOW, "DPOT UD" },
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+};
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+
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static void __init autcpu12_init(void)
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{
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clps711x_devices_init();
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@@ -160,6 +172,8 @@ static void __init autcpu12_init(void)
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static void __init autcpu12_init_late(void)
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{
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+ gpio_request_array(autcpu12_gpios, ARRAY_SIZE(autcpu12_gpios));
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+
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if (IS_ENABLED(MTD_NAND_GPIO) && IS_ENABLED(GPIO_GENERIC_PLATFORM)) {
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/* We are need both drivers to handle NAND */
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platform_device_register(&autcpu12_nand_pdev);
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