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@@ -673,18 +673,11 @@ static void iwl_set_pwr_vmain(struct iwl_trans *trans)
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#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
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#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
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-static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
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+static void iwl_apm_config(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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- u16 pci_lnk_ctl;
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-
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- pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL,
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- &pci_lnk_ctl);
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- return pci_lnk_ctl;
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-}
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+ u16 lctl;
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-static void iwl_apm_config(struct iwl_trans *trans)
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-{
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/*
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* HW bug W/A for instability in PCIe bus L0S->L1 transition.
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* Check if BIOS (or OS) enabled L1-ASPM on this device.
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@@ -693,8 +686,8 @@ static void iwl_apm_config(struct iwl_trans *trans)
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* If not (unlikely), enable L0S, so there is at least some
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* power savings, even without L1.
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*/
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- u16 lctl = iwl_pciexp_link_ctrl(trans);
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+ pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
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if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
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PCI_CFG_LINK_CTRL_VAL_L1_EN) {
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/* L1-ASPM enabled; disable(!) L0S */
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