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@@ -876,13 +876,13 @@ static ssize_t ca91cx42_master_read(struct vme_master_resource *image,
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* maximal configured data cycle is used and splits it
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* automatically for non-aligned addresses.
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*/
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- if ((int)addr & 0x1) {
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+ if ((uintptr_t)addr & 0x1) {
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*(u8 *)buf = ioread8(addr);
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done += 1;
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if (done == count)
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goto out;
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}
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- if ((int)addr & 0x2) {
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+ if ((uintptr_t)addr & 0x2) {
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if ((count - done) < 2) {
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*(u8 *)(buf + done) = ioread8(addr + done);
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done += 1;
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@@ -930,13 +930,13 @@ static ssize_t ca91cx42_master_write(struct vme_master_resource *image,
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/* Here we apply for the same strategy we do in master_read
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* function in order to assure D16 cycle when required.
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*/
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- if ((int)addr & 0x1) {
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+ if ((uintptr_t)addr & 0x1) {
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iowrite8(*(u8 *)buf, addr);
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done += 1;
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if (done == count)
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goto out;
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}
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- if ((int)addr & 0x2) {
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+ if ((uintptr_t)addr & 0x2) {
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if ((count - done) < 2) {
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iowrite8(*(u8 *)(buf + done), addr + done);
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done += 1;
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@@ -973,7 +973,8 @@ static unsigned int ca91cx42_master_rmw(struct vme_master_resource *image,
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unsigned int mask, unsigned int compare, unsigned int swap,
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loff_t offset)
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{
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- u32 pci_addr, result;
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+ u32 result;
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+ uintptr_t pci_addr;
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int i;
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struct ca91cx42_driver *bridge;
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struct device *dev;
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@@ -990,7 +991,7 @@ static unsigned int ca91cx42_master_rmw(struct vme_master_resource *image,
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/* Lock image */
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spin_lock(&image->lock);
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- pci_addr = (u32)image->kern_base + offset;
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+ pci_addr = (uintptr_t)image->kern_base + offset;
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/* Address must be 4-byte aligned */
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if (pci_addr & 0x3) {
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