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@@ -8,38 +8,30 @@ Required properties:
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- reg: Register location and size, for OMAP4+ as an array:
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<MPU access base address, size>,
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<L3 interconnect address, size>;
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+- reg-names: Array of strings associated with the address space
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- interrupts: Interrupt numbers for the McBSP port, as an array in case the
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McBSP IP have more interrupt lines:
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<OCP compliant irq>,
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<TX irq>,
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<RX irq>;
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+- interrupt-names: Array of strings associated with the interrupt numbers
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- interrupt-parent: The parent interrupt controller
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- ti,buffer-size: Size of the FIFO on the port (OMAP2430 and newer SoC)
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- ti,hwmods: Name of the hwmod associated to the McBSP port
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-Sidetone support for OMAP3 McBSP2 and 3 ports:
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-- sidetone { }: Within this section the following parameters are required:
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-- reg: Register location and size for the ST block
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-- interrupts: The interrupt number for the ST block
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-- interrupt-parent: The parent interrupt controller for the ST block
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-
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Example:
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mcbsp2: mcbsp@49022000 {
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compatible = "ti,omap3-mcbsp";
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- #address-cells = <1>;
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- #size-cells = <1>;
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- reg = <0x49022000 0xff>;
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- interrupts = <0 17 0x4>, /* OCP compliant interrup */
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- <0 62 0x4>, /* TX interrup */
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- <0 63 0x4>; /* RX interrup */
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+ reg = <0x49022000 0xff>,
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+ <0x49028000 0xff>;
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+ reg-names = "mpu", "sidetone";
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+ interrupts = <0 17 0x4>, /* OCP compliant interrupt */
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+ <0 62 0x4>, /* TX interrupt */
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+ <0 63 0x4>, /* RX interrupt */
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+ <0 4 0x4>; /* Sidetone */
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+ interrupt-names = "common", "tx", "rx", "sidetone";
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interrupt-parent = <&intc>;
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ti,buffer-size = <1280>;
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ti,hwmods = "mcbsp2";
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-
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- sidetone {
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- reg = <0x49028000 0xff>;
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- interrupts = <0 4 0x4>;
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- interrupt-parent = <&intc>;
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- };
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};
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