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@@ -89,12 +89,28 @@ static inline void pcibios_penalize_isa_irq(int irq, int active)
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#endif
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#ifdef CONFIG_PCI
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+/*
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+ * None of the SH PCI controllers support MWI, it is always treated as a
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+ * direct memory write.
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+ */
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+#define PCI_DISABLE_MWI
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+
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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enum pci_dma_burst_strategy *strat,
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unsigned long *strategy_parameter)
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{
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- *strat = PCI_DMA_BURST_INFINITY;
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- *strategy_parameter = ~0UL;
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+ unsigned long cacheline_size;
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+ u8 byte;
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+
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+ pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
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+
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+ if (byte == 0)
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+ cacheline_size = L1_CACHE_BYTES;
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+ else
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+ cacheline_size = byte << 2;
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+
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+ *strat = PCI_DMA_BURST_MULTIPLE;
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+ *strategy_parameter = cacheline_size;
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}
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#endif
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