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@@ -304,10 +304,20 @@ void flush_dcache_page(struct page *page)
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offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
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addr = mpnt->vm_start + offset;
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+ /* The TLB is the engine of coherence on parisc: The
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+ * CPU is entitled to speculate any page with a TLB
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+ * mapping, so here we kill the mapping then flush the
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+ * page along a special flush only alias mapping.
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+ * This guarantees that the page is no-longer in the
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+ * cache for any process and nor may it be
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+ * speculatively read in (until the user or kernel
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+ * specifically accesses it, of course) */
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+
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+ flush_tlb_page(mpnt, addr);
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if (old_addr == 0 || (old_addr & (SHMLBA - 1)) != (addr & (SHMLBA - 1))) {
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__flush_cache_page(mpnt, addr, page_to_phys(page));
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if (old_addr)
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- printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %s\n", old_addr, addr, mpnt->vm_file ? mpnt->vm_file->f_path.dentry->d_name.name : "(null)");
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+ printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %s\n", old_addr, addr, mpnt->vm_file ? (char *)mpnt->vm_file->f_path.dentry->d_name.name : "(null)");
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old_addr = addr;
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}
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}
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@@ -499,6 +509,7 @@ flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long
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{
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BUG_ON(!vma->vm_mm->context);
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+ flush_tlb_page(vma, vmaddr);
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__flush_cache_page(vma, vmaddr, page_to_phys(pfn_to_page(pfn)));
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}
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