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@@ -49,8 +49,6 @@
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/*
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* CSI registers
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*/
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-#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
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-#define DMA_DIMR 0x08 /* Interrupt mask Register */
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#define CSICR1 0x00 /* CSI Control Register 1 */
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#define CSISR 0x08 /* CSI Status Register */
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#define CSIRXR 0x10 /* CSI RxFIFO Register */
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@@ -784,7 +782,7 @@ static int __init mx1_camera_probe(struct platform_device *pdev)
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pcdev);
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imx_dma_config_channel(pcdev->dma_chan, IMX_DMA_TYPE_FIFO,
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- IMX_DMA_MEMSIZE_32, DMA_REQ_CSI_R, 0);
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+ IMX_DMA_MEMSIZE_32, MX1_DMA_REQ_CSI_R, 0);
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/* burst length : 16 words = 64 bytes */
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imx_dma_config_burstlen(pcdev->dma_chan, 0);
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@@ -798,8 +796,8 @@ static int __init mx1_camera_probe(struct platform_device *pdev)
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set_fiq_handler(&mx1_camera_sof_fiq_start, &mx1_camera_sof_fiq_end -
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&mx1_camera_sof_fiq_start);
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- regs.ARM_r8 = DMA_BASE + DMA_DIMR;
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- regs.ARM_r9 = DMA_BASE + DMA_CCR(pcdev->dma_chan);
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+ regs.ARM_r8 = (long)MX1_DMA_DIMR;
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+ regs.ARM_r9 = (long)MX1_DMA_CCR(pcdev->dma_chan);
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regs.ARM_r10 = (long)pcdev->base + CSICR1;
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regs.ARM_fp = (long)pcdev->base + CSISR;
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regs.ARM_sp = 1 << pcdev->dma_chan;
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