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@@ -81,26 +81,6 @@
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*/
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#define IWL49_FIRST_AMPDU_QUEUE 7
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-/* Time constants */
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-#define SHORT_SLOT_TIME 9
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-#define LONG_SLOT_TIME 20
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-
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-/* RSSI to dBm */
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-#define IWL49_RSSI_OFFSET 44
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-
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-
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-/* PCI registers */
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-#define PCI_CFG_RETRY_TIMEOUT 0x041
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-
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-/* PCI register values */
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-#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
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-#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
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-
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-#define IWL_NUM_SCAN_RATES (2)
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-
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-#define IWL_DEFAULT_TX_RETRY 15
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-
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-
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/* Sizes and addresses for instruction and data memory (SRAM) in
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* 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
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#define IWL49_RTC_INST_LOWER_BOUND (0x000000)
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@@ -393,10 +373,6 @@ static inline int iwl4965_hw_valid_rtc_data_addr(u32 addr)
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* location(s) in command (struct iwl4965_txpowertable_cmd).
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*/
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-/* Limit range of txpower output target to be between these values */
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-#define IWL_TX_POWER_TARGET_POWER_MIN (0) /* 0 dBm = 1 milliwatt */
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-#define IWL_TX_POWER_TARGET_POWER_MAX (16) /* 16 dBm */
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-
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/**
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* When MIMO is used (2 transmitters operating simultaneously), driver should
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* limit each transmitter to deliver a max of 3 dB below the regulatory limit
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