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@@ -1160,14 +1160,25 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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EVERGREEN_MAX_BACKENDS_MASK));
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break;
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}
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- } else
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- gb_backend_map =
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- evergreen_get_tile_pipe_to_backend_map(rdev,
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- rdev->config.evergreen.max_tile_pipes,
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- rdev->config.evergreen.max_backends,
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- ((EVERGREEN_MAX_BACKENDS_MASK <<
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- rdev->config.evergreen.max_backends) &
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- EVERGREEN_MAX_BACKENDS_MASK));
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+ } else {
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+ switch (rdev->family) {
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+ case CHIP_CYPRESS:
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+ case CHIP_HEMLOCK:
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+ gb_backend_map = 0x66442200;
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+ break;
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+ case CHIP_JUNIPER:
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+ gb_backend_map = 0x00006420;
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+ break;
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+ default:
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+ gb_backend_map =
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+ evergreen_get_tile_pipe_to_backend_map(rdev,
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+ rdev->config.evergreen.max_tile_pipes,
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+ rdev->config.evergreen.max_backends,
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+ ((EVERGREEN_MAX_BACKENDS_MASK <<
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+ rdev->config.evergreen.max_backends) &
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+ EVERGREEN_MAX_BACKENDS_MASK));
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+ }
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+ }
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rdev->config.evergreen.tile_config = gb_addr_config;
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WREG32(GB_BACKEND_MAP, gb_backend_map);
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