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@@ -40,53 +40,8 @@
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#include <mach/i2c.h>
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#include <mach/nand.h>
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-#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
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- defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
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-#define HAS_ATA 1
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-#else
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-#define HAS_ATA 0
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-#endif
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-
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-#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x20008000
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-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
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-
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#define NAND_BLOCK_SIZE SZ_128K
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-/* CPLD Register 0 bits to control ATA */
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-#define DM646X_EVM_ATA_RST BIT(0)
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-#define DM646X_EVM_ATA_PWD BIT(1)
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-
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-#define DM646X_EVM_PHY_MASK (0x2)
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-#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
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-
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-#define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
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-#define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
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-#define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
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-#define VCH2CLK_SYSCLK8 (BIT(9))
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-#define VCH2CLK_AUXCLK (BIT(9) | BIT(8))
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-#define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
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-#define VCH3CLK_SYSCLK8 (BIT(13))
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-#define VCH3CLK_AUXCLK (BIT(14) | BIT(13))
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-
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-#define VIDCH2CLK (BIT(10))
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-#define VIDCH3CLK (BIT(11))
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-#define VIDCH1CLK (BIT(4))
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-#define TVP7002_INPUT (BIT(4))
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-#define TVP5147_INPUT (~BIT(4))
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-#define VPIF_INPUT_ONE_CHANNEL (BIT(5))
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-#define VPIF_INPUT_TWO_CHANNEL (~BIT(5))
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-#define TVP5147_CH0 "tvp514x-0"
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-#define TVP5147_CH1 "tvp514x-1"
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-
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-static void __iomem *vpif_vidclkctl_reg;
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-static void __iomem *vpif_vsclkdis_reg;
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-/* spin lock for updating above registers */
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-static spinlock_t vpif_reg_lock;
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-
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-static struct davinci_uart_config uart_config __initdata = {
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- .enabled_uarts = (1 << 0),
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-};
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-
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/* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
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* and U-Boot environment this avoids dependency on any particular combination
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* of UBL, U-Boot or flashing tools etc.
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@@ -120,6 +75,9 @@ static struct davinci_nand_pdata davinci_nand_data = {
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.options = 0,
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};
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+#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x20008000
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+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
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+
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static struct resource davinci_nand_resources[] = {
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{
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.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
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@@ -144,6 +102,17 @@ static struct platform_device davinci_nand_device = {
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},
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};
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+#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
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+ defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
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+#define HAS_ATA 1
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+#else
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+#define HAS_ATA 0
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+#endif
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+
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+/* CPLD Register 0 bits to control ATA */
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+#define DM646X_EVM_ATA_RST BIT(0)
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+#define DM646X_EVM_ATA_PWD BIT(1)
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+
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/* CPLD Register 0 Client: used for I/O Control */
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static int cpld_reg0_probe(struct i2c_client *client,
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const struct i2c_device_id *id)
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@@ -424,6 +393,30 @@ static struct davinci_i2c_platform_data i2c_pdata = {
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.bus_delay = 0 /* usec */,
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};
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+#define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
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+#define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
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+#define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
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+#define VCH2CLK_SYSCLK8 (BIT(9))
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+#define VCH2CLK_AUXCLK (BIT(9) | BIT(8))
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+#define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
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+#define VCH3CLK_SYSCLK8 (BIT(13))
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+#define VCH3CLK_AUXCLK (BIT(14) | BIT(13))
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+
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+#define VIDCH2CLK (BIT(10))
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+#define VIDCH3CLK (BIT(11))
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+#define VIDCH1CLK (BIT(4))
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+#define TVP7002_INPUT (BIT(4))
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+#define TVP5147_INPUT (~BIT(4))
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+#define VPIF_INPUT_ONE_CHANNEL (BIT(5))
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+#define VPIF_INPUT_TWO_CHANNEL (~BIT(5))
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+#define TVP5147_CH0 "tvp514x-0"
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+#define TVP5147_CH1 "tvp514x-1"
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+
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+static void __iomem *vpif_vidclkctl_reg;
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+static void __iomem *vpif_vsclkdis_reg;
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+/* spin lock for updating above registers */
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+static spinlock_t vpif_reg_lock;
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+
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static int set_vpif_clock(int mux_mode, int hd)
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{
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unsigned long flags;
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@@ -690,6 +683,13 @@ static void __init davinci_map_io(void)
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dm646x_init();
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}
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+static struct davinci_uart_config uart_config __initdata = {
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+ .enabled_uarts = (1 << 0),
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+};
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+
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+#define DM646X_EVM_PHY_MASK (0x2)
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+#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
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+
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static __init void evm_init(void)
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{
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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