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@@ -0,0 +1,294 @@
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+/*
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+ * Performance events - AMD IBS
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+ *
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+ * Copyright (C) 2011 Advanced Micro Devices, Inc., Robert Richter
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+ *
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+ * For licencing details see kernel-base/COPYING
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+ */
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+
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+#include <linux/perf_event.h>
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+#include <linux/module.h>
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+#include <linux/pci.h>
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+
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+#include <asm/apic.h>
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+
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+static u32 ibs_caps;
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+
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+#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
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+
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+static struct pmu perf_ibs;
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+
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+static int perf_ibs_init(struct perf_event *event)
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+{
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+ if (perf_ibs.type != event->attr.type)
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+ return -ENOENT;
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+ return 0;
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+}
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+
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+static int perf_ibs_add(struct perf_event *event, int flags)
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+{
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+ return 0;
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+}
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+
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+static void perf_ibs_del(struct perf_event *event, int flags)
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+{
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+}
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+
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+static struct pmu perf_ibs = {
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+ .event_init= perf_ibs_init,
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+ .add= perf_ibs_add,
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+ .del= perf_ibs_del,
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+};
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+
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+static __init int perf_event_ibs_init(void)
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+{
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+ if (!ibs_caps)
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+ return -ENODEV; /* ibs not supported by the cpu */
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+
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+ perf_pmu_register(&perf_ibs, "ibs", -1);
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+ printk(KERN_INFO "perf: AMD IBS detected (0x%08x)\n", ibs_caps);
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+
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+ return 0;
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+}
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+
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+#else /* defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) */
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+
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+static __init int perf_event_ibs_init(void) { return 0; }
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+
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+#endif
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+
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+/* IBS - apic initialization, for perf and oprofile */
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+
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+static __init u32 __get_ibs_caps(void)
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+{
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+ u32 caps;
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+ unsigned int max_level;
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+
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+ if (!boot_cpu_has(X86_FEATURE_IBS))
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+ return 0;
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+
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+ /* check IBS cpuid feature flags */
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+ max_level = cpuid_eax(0x80000000);
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+ if (max_level < IBS_CPUID_FEATURES)
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+ return IBS_CAPS_DEFAULT;
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+
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+ caps = cpuid_eax(IBS_CPUID_FEATURES);
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+ if (!(caps & IBS_CAPS_AVAIL))
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+ /* cpuid flags not valid */
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+ return IBS_CAPS_DEFAULT;
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+
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+ return caps;
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+}
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+
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+u32 get_ibs_caps(void)
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+{
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+ return ibs_caps;
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+}
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+
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+EXPORT_SYMBOL(get_ibs_caps);
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+
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+static inline int get_eilvt(int offset)
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+{
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+ return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
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+}
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+
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+static inline int put_eilvt(int offset)
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+{
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+ return !setup_APIC_eilvt(offset, 0, 0, 1);
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+}
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+
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+/*
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+ * Check and reserve APIC extended interrupt LVT offset for IBS if available.
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+ */
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+static inline int ibs_eilvt_valid(void)
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+{
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+ int offset;
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+ u64 val;
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+ int valid = 0;
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+
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+ preempt_disable();
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+
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+ rdmsrl(MSR_AMD64_IBSCTL, val);
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+ offset = val & IBSCTL_LVT_OFFSET_MASK;
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+
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+ if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
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+ pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
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+ smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
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+ goto out;
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+ }
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+
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+ if (!get_eilvt(offset)) {
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+ pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
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+ smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
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+ goto out;
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+ }
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+
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+ valid = 1;
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+out:
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+ preempt_enable();
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+
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+ return valid;
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+}
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+
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+static int setup_ibs_ctl(int ibs_eilvt_off)
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+{
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+ struct pci_dev *cpu_cfg;
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+ int nodes;
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+ u32 value = 0;
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+
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+ nodes = 0;
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+ cpu_cfg = NULL;
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+ do {
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+ cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
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+ PCI_DEVICE_ID_AMD_10H_NB_MISC,
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+ cpu_cfg);
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+ if (!cpu_cfg)
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+ break;
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+ ++nodes;
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+ pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
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+ | IBSCTL_LVT_OFFSET_VALID);
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+ pci_read_config_dword(cpu_cfg, IBSCTL, &value);
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+ if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
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+ pci_dev_put(cpu_cfg);
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+ printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
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+ "IBSCTL = 0x%08x\n", value);
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+ return -EINVAL;
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+ }
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+ } while (1);
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+
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+ if (!nodes) {
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+ printk(KERN_DEBUG "No CPU node configured for IBS\n");
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+ return -ENODEV;
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+ }
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+
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+ return 0;
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+}
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+
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+/*
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+ * This runs only on the current cpu. We try to find an LVT offset and
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+ * setup the local APIC. For this we must disable preemption. On
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+ * success we initialize all nodes with this offset. This updates then
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+ * the offset in the IBS_CTL per-node msr. The per-core APIC setup of
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+ * the IBS interrupt vector is handled by perf_ibs_cpu_notifier that
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+ * is using the new offset.
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+ */
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+static int force_ibs_eilvt_setup(void)
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+{
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+ int offset;
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+ int ret;
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+
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+ preempt_disable();
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+ /* find the next free available EILVT entry, skip offset 0 */
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+ for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
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+ if (get_eilvt(offset))
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+ break;
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+ }
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+ preempt_enable();
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+
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+ if (offset == APIC_EILVT_NR_MAX) {
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+ printk(KERN_DEBUG "No EILVT entry available\n");
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+ return -EBUSY;
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+ }
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+
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+ ret = setup_ibs_ctl(offset);
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+ if (ret)
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+ goto out;
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+
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+ if (!ibs_eilvt_valid()) {
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+ ret = -EFAULT;
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+ goto out;
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+ }
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+
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+ pr_err(FW_BUG "using offset %d for IBS interrupts\n", offset);
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+ pr_err(FW_BUG "workaround enabled for IBS LVT offset\n");
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+
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+ return 0;
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+out:
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+ preempt_disable();
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+ put_eilvt(offset);
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+ preempt_enable();
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+ return ret;
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+}
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+
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+static inline int get_ibs_lvt_offset(void)
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+{
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+ u64 val;
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+
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+ rdmsrl(MSR_AMD64_IBSCTL, val);
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+ if (!(val & IBSCTL_LVT_OFFSET_VALID))
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+ return -EINVAL;
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+
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+ return val & IBSCTL_LVT_OFFSET_MASK;
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+}
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+
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+static void setup_APIC_ibs(void *dummy)
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+{
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+ int offset;
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+
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+ offset = get_ibs_lvt_offset();
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+ if (offset < 0)
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+ goto failed;
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+
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+ if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
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+ return;
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+failed:
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+ pr_warn("perf: IBS APIC setup failed on cpu #%d\n",
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+ smp_processor_id());
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+}
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+
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+static void clear_APIC_ibs(void *dummy)
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+{
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+ int offset;
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+
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+ offset = get_ibs_lvt_offset();
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+ if (offset >= 0)
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+ setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
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+}
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+
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+static int __cpuinit
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+perf_ibs_cpu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
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+{
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+ switch (action & ~CPU_TASKS_FROZEN) {
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+ case CPU_STARTING:
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+ setup_APIC_ibs(NULL);
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+ break;
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+ case CPU_DYING:
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+ clear_APIC_ibs(NULL);
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ return NOTIFY_OK;
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+}
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+
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+static __init int amd_ibs_init(void)
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+{
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+ u32 caps;
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+ int ret;
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+
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+ caps = __get_ibs_caps();
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+ if (!caps)
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+ return -ENODEV; /* ibs not supported by the cpu */
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+
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+ if (!ibs_eilvt_valid()) {
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+ ret = force_ibs_eilvt_setup();
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+ if (ret) {
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+ pr_err("Failed to setup IBS, %d\n", ret);
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+ return ret;
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+ }
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+ }
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+
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+ get_online_cpus();
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+ ibs_caps = caps;
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+ /* make ibs_caps visible to other cpus: */
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+ smp_mb();
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+ perf_cpu_notifier(perf_ibs_cpu_notifier);
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+ smp_call_function(setup_APIC_ibs, NULL, 1);
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+ put_online_cpus();
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+
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+ return perf_event_ibs_init();
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+}
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+
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+/* Since we need the pci subsystem to init ibs we can't do this earlier: */
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+device_initcall(amd_ibs_init);
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Robert Richter