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@@ -18,6 +18,63 @@ struct amd64_pvt;
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static struct mem_ctl_info *mci_lookup[MAX_NUMNODES];
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static struct amd64_pvt *pvt_lookup[MAX_NUMNODES];
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+/*
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+ * See F2x80 for K8 and F2x[1,0]80 for Fam10 and later. The table below is only
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+ * for DDR2 DRAM mapping.
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+ */
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+u32 revf_quad_ddr2_shift[] = {
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+ 0, /* 0000b NULL DIMM (128mb) */
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+ 28, /* 0001b 256mb */
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+ 29, /* 0010b 512mb */
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+ 29, /* 0011b 512mb */
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+ 29, /* 0100b 512mb */
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+ 30, /* 0101b 1gb */
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+ 30, /* 0110b 1gb */
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+ 31, /* 0111b 2gb */
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+ 31, /* 1000b 2gb */
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+ 32, /* 1001b 4gb */
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+ 32, /* 1010b 4gb */
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+ 33, /* 1011b 8gb */
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+ 0, /* 1100b future */
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+ 0, /* 1101b future */
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+ 0, /* 1110b future */
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+ 0 /* 1111b future */
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+};
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+
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+/*
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+ * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing
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+ * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
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+ * or higher value'.
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+ *
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+ *FIXME: Produce a better mapping/linearisation.
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+ */
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+
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+struct scrubrate scrubrates[] = {
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+ { 0x01, 1600000000UL},
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+ { 0x02, 800000000UL},
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+ { 0x03, 400000000UL},
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+ { 0x04, 200000000UL},
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+ { 0x05, 100000000UL},
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+ { 0x06, 50000000UL},
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+ { 0x07, 25000000UL},
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+ { 0x08, 12284069UL},
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+ { 0x09, 6274509UL},
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+ { 0x0A, 3121951UL},
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+ { 0x0B, 1560975UL},
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+ { 0x0C, 781440UL},
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+ { 0x0D, 390720UL},
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+ { 0x0E, 195300UL},
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+ { 0x0F, 97650UL},
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+ { 0x10, 48854UL},
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+ { 0x11, 24427UL},
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+ { 0x12, 12213UL},
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+ { 0x13, 6101UL},
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+ { 0x14, 3051UL},
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+ { 0x15, 1523UL},
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+ { 0x16, 761UL},
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+ { 0x00, 0UL}, /* scrubbing off */
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+};
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+
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/*
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* Memory scrubber control interface. For K8, memory scrubbing is handled by
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* hardware and can involve L2 cache, dcache as well as the main memory. With
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@@ -1101,8 +1158,8 @@ static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
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u32 page, offset;
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/* Extract the syndrome parts and form a 16-bit syndrome */
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- syndrome = EXTRACT_HIGH_SYNDROME(info->nbsl) << 8;
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- syndrome |= EXTRACT_LOW_SYNDROME(info->nbsh);
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+ syndrome = HIGH_SYNDROME(info->nbsl) << 8;
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+ syndrome |= LOW_SYNDROME(info->nbsh);
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/* CHIPKILL enabled */
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if (info->nbcfg & K8_NBCFG_CHIPKILL) {
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@@ -1701,8 +1758,8 @@ static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
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if (csrow >= 0) {
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error_address_to_page_and_offset(sys_addr, &page, &offset);
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- syndrome = EXTRACT_HIGH_SYNDROME(info->nbsl) << 8;
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- syndrome |= EXTRACT_LOW_SYNDROME(info->nbsh);
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+ syndrome = HIGH_SYNDROME(info->nbsl) << 8;
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+ syndrome |= LOW_SYNDROME(info->nbsh);
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/*
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* Is CHIPKILL on? If so, then we can attempt to use the
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@@ -2155,36 +2212,22 @@ static int amd64_get_error_info(struct mem_ctl_info *mci,
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static inline void amd64_decode_gart_tlb_error(struct mem_ctl_info *mci,
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struct amd64_error_info_regs *info)
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{
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- u32 err_code;
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- u32 ec_tt; /* error code transaction type (2b) */
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- u32 ec_ll; /* error code cache level (2b) */
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-
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- err_code = EXTRACT_ERROR_CODE(info->nbsl);
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- ec_ll = EXTRACT_LL_CODE(err_code);
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- ec_tt = EXTRACT_TT_CODE(err_code);
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+ u32 ec = ERROR_CODE(info->nbsl);
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amd64_mc_printk(mci, KERN_ERR,
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"GART TLB event: transaction type(%s), "
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- "cache level(%s)\n", tt_msgs[ec_tt], ll_msgs[ec_ll]);
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+ "cache level(%s)\n", TT_MSG(ec), LL_MSG(ec));
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}
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static inline void amd64_decode_mem_cache_error(struct mem_ctl_info *mci,
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struct amd64_error_info_regs *info)
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{
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- u32 err_code;
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- u32 ec_rrrr; /* error code memory transaction (4b) */
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- u32 ec_tt; /* error code transaction type (2b) */
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- u32 ec_ll; /* error code cache level (2b) */
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-
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- err_code = EXTRACT_ERROR_CODE(info->nbsl);
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- ec_ll = EXTRACT_LL_CODE(err_code);
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- ec_tt = EXTRACT_TT_CODE(err_code);
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- ec_rrrr = EXTRACT_RRRR_CODE(err_code);
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+ u32 ec = ERROR_CODE(info->nbsl);
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amd64_mc_printk(mci, KERN_ERR,
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"cache hierarchy error: memory transaction type(%s), "
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"transaction type(%s), cache level(%s)\n",
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- rrrr_msgs[ec_rrrr], tt_msgs[ec_tt], ll_msgs[ec_ll]);
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+ RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
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}
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@@ -2264,21 +2307,8 @@ static void amd64_handle_ue(struct mem_ctl_info *mci,
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static void amd64_decode_bus_error(struct mem_ctl_info *mci,
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struct amd64_error_info_regs *info)
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{
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- u32 err_code, ext_ec;
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- u32 ec_pp; /* error code participating processor (2p) */
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- u32 ec_to; /* error code timed out (1b) */
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- u32 ec_rrrr; /* error code memory transaction (4b) */
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- u32 ec_ii; /* error code memory or I/O (2b) */
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- u32 ec_ll; /* error code cache level (2b) */
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-
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- ext_ec = EXTRACT_EXT_ERROR_CODE(info->nbsl);
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- err_code = EXTRACT_ERROR_CODE(info->nbsl);
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-
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- ec_ll = EXTRACT_LL_CODE(err_code);
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- ec_ii = EXTRACT_II_CODE(err_code);
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- ec_rrrr = EXTRACT_RRRR_CODE(err_code);
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- ec_to = EXTRACT_TO_CODE(err_code);
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- ec_pp = EXTRACT_PP_CODE(err_code);
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+ u32 ec = ERROR_CODE(info->nbsl);
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+ u32 xec = EXT_ERROR_CODE(info->nbsl);
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amd64_mc_printk(mci, KERN_ERR,
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"BUS ERROR:\n"
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@@ -2286,20 +2316,17 @@ static void amd64_decode_bus_error(struct mem_ctl_info *mci,
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" participating processor(%s)\n"
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" memory transaction type(%s)\n"
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" cache level(%s) Error Found by: %s\n",
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- to_msgs[ec_to],
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- ii_msgs[ec_ii],
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- pp_msgs[ec_pp],
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- rrrr_msgs[ec_rrrr],
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- ll_msgs[ec_ll],
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+ TO_MSG(ec), II_MSG(ec), PP_MSG(ec), RRRR_MSG(ec), LL_MSG(ec),
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(info->nbsh & K8_NBSH_ERR_SCRUBER) ?
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"Scrubber" : "Normal Operation");
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- /* If this was an 'observed' error, early out */
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- if (ec_pp == K8_NBSL_PP_OBS)
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- return; /* We aren't the node involved */
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+
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+ /* Bail early out if this was an 'observed' error */
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+ if (PP(ec) == K8_NBSL_PP_OBS)
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+ return;
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/* Parse out the extended error code for ECC events */
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- switch (ext_ec) {
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+ switch (xec) {
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/* F10 changed to one Extended ECC error code */
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case F10_NBSL_EXT_ERR_RES: /* Reserved field */
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case F10_NBSL_EXT_ERR_ECC: /* F10 ECC ext err code */
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@@ -2379,7 +2406,7 @@ int amd64_process_error_info(struct mem_ctl_info *mci,
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(regs->nbsh & K8_NBSH_CORE3) ? "True" : "False");
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- err_code = EXTRACT_ERROR_CODE(regs->nbsl);
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+ err_code = ERROR_CODE(regs->nbsl);
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/* Determine which error type:
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* 1) GART errors - non-fatal, developmental events
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@@ -2387,7 +2414,7 @@ int amd64_process_error_info(struct mem_ctl_info *mci,
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* 3) BUS errors
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* 4) Unknown error
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*/
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- if (TEST_TLB_ERROR(err_code)) {
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+ if (TLB_ERROR(err_code)) {
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/*
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* GART errors are intended to help graphics driver developers
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* to detect bad GART PTEs. It is recommended by AMD to disable
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@@ -2411,10 +2438,10 @@ int amd64_process_error_info(struct mem_ctl_info *mci,
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debugf1("GART TLB error\n");
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amd64_decode_gart_tlb_error(mci, info);
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- } else if (TEST_MEM_ERROR(err_code)) {
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+ } else if (MEM_ERROR(err_code)) {
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debugf1("Memory/Cache error\n");
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amd64_decode_mem_cache_error(mci, info);
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- } else if (TEST_BUS_ERROR(err_code)) {
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+ } else if (BUS_ERROR(err_code)) {
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debugf1("Bus (Link/DRAM) error\n");
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amd64_decode_bus_error(mci, info);
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} else {
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@@ -2424,21 +2451,10 @@ int amd64_process_error_info(struct mem_ctl_info *mci,
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err_code);
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}
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- ext_ec = EXTRACT_EXT_ERROR_CODE(regs->nbsl);
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+ ext_ec = EXT_ERROR_CODE(regs->nbsl);
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amd64_mc_printk(mci, KERN_ERR,
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"ExtErr=(0x%x) %s\n", ext_ec, ext_msgs[ext_ec]);
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- if (((ext_ec >= F10_NBSL_EXT_ERR_CRC &&
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- ext_ec <= F10_NBSL_EXT_ERR_TGT) ||
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- (ext_ec == F10_NBSL_EXT_ERR_RMW)) &&
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- EXTRACT_LDT_LINK(info->nbsh)) {
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-
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- amd64_mc_printk(mci, KERN_ERR,
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- "Error on hypertransport link: %s\n",
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- htlink_msgs[
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- EXTRACT_LDT_LINK(info->nbsh)]);
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- }
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-
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/*
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* Check the UE bit of the NB status high register, if set generate some
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* logs. If NOT a GART error, then process the event as a NO-INFO event.
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