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@@ -53,6 +53,18 @@
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#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
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#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
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+static int ksz_config_flags(struct phy_device *phydev)
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+{
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+ int regval;
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+
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+ if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
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+ regval = phy_read(phydev, MII_KSZPHY_CTRL);
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+ regval |= KSZ8051_RMII_50MHZ_CLK;
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+ return phy_write(phydev, MII_KSZPHY_CTRL, regval);
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+ }
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+ return 0;
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+}
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+
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static int kszphy_ack_interrupt(struct phy_device *phydev)
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{
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/* bit[7..0] int status, which is a read and clear register. */
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@@ -114,22 +126,19 @@ static int kszphy_config_init(struct phy_device *phydev)
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static int ksz8021_config_init(struct phy_device *phydev)
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{
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+ int rc;
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const u16 val = KSZPHY_OMSO_B_CAST_OFF | KSZPHY_OMSO_RMII_OVERRIDE;
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phy_write(phydev, MII_KSZPHY_OMSO, val);
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- return 0;
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+ rc = ksz_config_flags(phydev);
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+ return rc < 0 ? rc : 0;
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}
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static int ks8051_config_init(struct phy_device *phydev)
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{
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- int regval;
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-
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- if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
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- regval = phy_read(phydev, MII_KSZPHY_CTRL);
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- regval |= KSZ8051_RMII_50MHZ_CLK;
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- phy_write(phydev, MII_KSZPHY_CTRL, regval);
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- }
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+ int rc;
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- return 0;
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+ rc = ksz_config_flags(phydev);
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+ return rc < 0 ? rc : 0;
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}
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#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
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