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@@ -26,14 +26,14 @@
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/**
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- * mei_reg_read - Reads 32bit data from the mei device
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+ * mei_me_reg_read - Reads 32bit data from the mei device
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*
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* @dev: the device structure
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* @offset: offset from which to read the data
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*
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* returns register value (u32)
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*/
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-static inline u32 mei_reg_read(const struct mei_me_hw *hw,
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+static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
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unsigned long offset)
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{
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return ioread32(hw->mem_addr + offset);
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@@ -41,20 +41,20 @@ static inline u32 mei_reg_read(const struct mei_me_hw *hw,
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/**
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- * mei_reg_write - Writes 32bit data to the mei device
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+ * mei_me_reg_write - Writes 32bit data to the mei device
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*
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* @dev: the device structure
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* @offset: offset from which to write the data
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* @value: register value to write (u32)
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*/
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-static inline void mei_reg_write(const struct mei_me_hw *hw,
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+static inline void mei_me_reg_write(const struct mei_me_hw *hw,
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unsigned long offset, u32 value)
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{
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iowrite32(value, hw->mem_addr + offset);
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}
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/**
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- * mei_mecbrw_read - Reads 32bit data from ME circular buffer
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+ * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
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* read window register
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*
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* @dev: the device structure
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@@ -63,18 +63,18 @@ static inline void mei_reg_write(const struct mei_me_hw *hw,
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*/
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static u32 mei_me_mecbrw_read(const struct mei_device *dev)
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{
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- return mei_reg_read(to_me_hw(dev), ME_CB_RW);
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+ return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
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}
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/**
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- * mei_mecsr_read - Reads 32bit data from the ME CSR
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+ * mei_me_mecsr_read - Reads 32bit data from the ME CSR
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*
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* @dev: the device structure
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*
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* returns ME_CSR_HA register value (u32)
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*/
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-static inline u32 mei_mecsr_read(const struct mei_me_hw *hw)
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+static inline u32 mei_me_mecsr_read(const struct mei_me_hw *hw)
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{
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- return mei_reg_read(hw, ME_CSR_HA);
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+ return mei_me_reg_read(hw, ME_CSR_HA);
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}
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/**
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@@ -86,7 +86,7 @@ static inline u32 mei_mecsr_read(const struct mei_me_hw *hw)
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*/
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static inline u32 mei_hcsr_read(const struct mei_me_hw *hw)
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{
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- return mei_reg_read(hw, H_CSR);
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+ return mei_me_reg_read(hw, H_CSR);
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}
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/**
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@@ -98,7 +98,7 @@ static inline u32 mei_hcsr_read(const struct mei_me_hw *hw)
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static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr)
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{
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hcsr &= ~H_IS;
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- mei_reg_write(hw, H_CSR, hcsr);
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+ mei_me_reg_write(hw, H_CSR, hcsr);
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}
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@@ -123,7 +123,7 @@ static void mei_me_intr_clear(struct mei_device *dev)
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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if ((hcsr & H_IS) == H_IS)
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- mei_reg_write(hw, H_CSR, hcsr);
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+ mei_me_reg_write(hw, H_CSR, hcsr);
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}
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/**
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* mei_me_intr_enable - enables mei device interrupts
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@@ -228,7 +228,7 @@ static bool mei_me_host_is_ready(struct mei_device *dev)
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static bool mei_me_hw_is_ready(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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- hw->me_hw_state = mei_mecsr_read(hw);
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+ hw->me_hw_state = mei_me_mecsr_read(hw);
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return (hw->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA;
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}
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@@ -354,16 +354,16 @@ static int mei_me_write_message(struct mei_device *dev,
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if (empty_slots < 0 || dw_cnt > empty_slots)
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return -EIO;
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- mei_reg_write(hw, H_CB_WW, *((u32 *) header));
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+ mei_me_reg_write(hw, H_CB_WW, *((u32 *) header));
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for (i = 0; i < length / 4; i++)
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- mei_reg_write(hw, H_CB_WW, reg_buf[i]);
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+ mei_me_reg_write(hw, H_CB_WW, reg_buf[i]);
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rem = length & 0x3;
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if (rem > 0) {
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u32 reg = 0;
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memcpy(®, &buf[length - rem], rem);
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- mei_reg_write(hw, H_CB_WW, reg);
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+ mei_me_reg_write(hw, H_CB_WW, reg);
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}
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hcsr = mei_hcsr_read(hw) | H_IG;
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@@ -387,7 +387,7 @@ static int mei_me_count_full_read_slots(struct mei_device *dev)
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char read_ptr, write_ptr;
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unsigned char buffer_depth, filled_slots;
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- hw->me_hw_state = mei_mecsr_read(hw);
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+ hw->me_hw_state = mei_me_mecsr_read(hw);
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buffer_depth = (unsigned char)((hw->me_hw_state & ME_CBD_HRA) >> 24);
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read_ptr = (char) ((hw->me_hw_state & ME_CBRP_HRA) >> 8);
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write_ptr = (char) ((hw->me_hw_state & ME_CBWP_HRA) >> 16);
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@@ -447,7 +447,7 @@ irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
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return IRQ_NONE;
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/* clear H_IS bit in H_CSR */
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- mei_reg_write(hw, H_CSR, csr_reg);
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+ mei_me_reg_write(hw, H_CSR, csr_reg);
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return IRQ_WAKE_THREAD;
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}
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