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@@ -739,7 +739,6 @@ int iwl4965_hw_nic_init(struct iwl_priv *priv)
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{
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{
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unsigned long flags;
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unsigned long flags;
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struct iwl4965_rx_queue *rxq = &priv->rxq;
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struct iwl4965_rx_queue *rxq = &priv->rxq;
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- u8 rev_id;
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u8 val_link;
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u8 val_link;
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u32 val;
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u32 val;
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int ret;
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int ret;
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@@ -751,18 +750,11 @@ int iwl4965_hw_nic_init(struct iwl_priv *priv)
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iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
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iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
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spin_unlock_irqrestore(&priv->lock, flags);
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spin_unlock_irqrestore(&priv->lock, flags);
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- /* Determine HW type */
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- ret = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
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- if (ret)
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- return ret;
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-
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- IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
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-
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ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
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ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
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spin_lock_irqsave(&priv->lock, flags);
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spin_lock_irqsave(&priv->lock, flags);
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- if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
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+ if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
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pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
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pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
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/* Enable No Snoop field */
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/* Enable No Snoop field */
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pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
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pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
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