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@@ -0,0 +1,362 @@
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+/*
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+ * drivers/char/watchdog/pnx4008_wdt.c
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+ *
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+ * Watchdog driver for PNX4008 board
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+ *
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+ * Authors: Dmitry Chigirev <source@mvista.com>,
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+ * Vitaly Wool <vitalywool@gmail.com>
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+ * Based on sa1100 driver,
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+ * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
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+ *
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+ * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
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+ * the terms of the GNU General Public License version 2. This program
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+ * is licensed "as is" without any warranty of any kind, whether express
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+ * or implied.
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+ */
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+
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+#include <linux/config.h>
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+#include <linux/module.h>
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+#include <linux/moduleparam.h>
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+#include <linux/types.h>
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+#include <linux/kernel.h>
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+#include <linux/fs.h>
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+#include <linux/miscdevice.h>
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+#include <linux/watchdog.h>
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+#include <linux/init.h>
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+#include <linux/bitops.h>
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+#include <linux/ioport.h>
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+#include <linux/device.h>
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+#include <linux/platform_device.h>
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+#include <linux/clk.h>
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+#include <linux/spinlock.h>
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+
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+#include <asm/hardware.h>
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+#include <asm/uaccess.h>
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+#include <asm/io.h>
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+
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+#define MODULE_NAME "PNX4008-WDT: "
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+
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+/* WatchDog Timer - Chapter 23 Page 207 */
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+
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+#define DEFAULT_HEARTBEAT 19
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+#define MAX_HEARTBEAT 60
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+
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+/* Watchdog timer register set definition */
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+#define WDTIM_INT(p) ((p) + 0x0)
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+#define WDTIM_CTRL(p) ((p) + 0x4)
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+#define WDTIM_COUNTER(p) ((p) + 0x8)
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+#define WDTIM_MCTRL(p) ((p) + 0xC)
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+#define WDTIM_MATCH0(p) ((p) + 0x10)
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+#define WDTIM_EMR(p) ((p) + 0x14)
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+#define WDTIM_PULSE(p) ((p) + 0x18)
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+#define WDTIM_RES(p) ((p) + 0x1C)
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+
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+/* WDTIM_INT bit definitions */
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+#define MATCH_INT 1
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+
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+/* WDTIM_CTRL bit definitions */
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+#define COUNT_ENAB 1
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+#define RESET_COUNT (1<<1)
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+#define DEBUG_EN (1<<2)
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+
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+/* WDTIM_MCTRL bit definitions */
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+#define MR0_INT 1
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+#undef RESET_COUNT0
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+#define RESET_COUNT0 (1<<2)
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+#define STOP_COUNT0 (1<<2)
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+#define M_RES1 (1<<3)
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+#define M_RES2 (1<<4)
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+#define RESFRC1 (1<<5)
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+#define RESFRC2 (1<<6)
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+
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+/* WDTIM_EMR bit definitions */
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+#define EXT_MATCH0 1
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+#define MATCH_OUTPUT_HIGH (2<<4) /*a MATCH_CTRL setting */
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+
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+/* WDTIM_RES bit definitions */
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+#define WDOG_RESET 1 /* read only */
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+
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+#define WDOG_COUNTER_RATE 13000000 /*the counter clock is 13 MHz fixed */
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+
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+static int nowayout = WATCHDOG_NOWAYOUT;
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+static int heartbeat = DEFAULT_HEARTBEAT;
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+
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+static spinlock_t io_lock;
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+static unsigned long wdt_status;
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+#define WDT_IN_USE 0
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+#define WDT_OK_TO_CLOSE 1
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+#define WDT_REGION_INITED 2
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+#define WDT_DEVICE_INITED 3
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+
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+static unsigned long boot_status;
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+
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+static struct resource *wdt_mem;
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+static void __iomem *wdt_base;
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+struct clk *wdt_clk;
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+
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+static void wdt_enable(void)
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+{
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+ spin_lock(&io_lock);
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+
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+ if (wdt_clk)
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+ clk_set_rate(wdt_clk, 1);
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+
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+ /* stop counter, initiate counter reset */
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+ __raw_writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
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+ /*wait for reset to complete. 100% guarantee event */
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+ while (__raw_readl(WDTIM_COUNTER(wdt_base)))
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+ cpu_relax();
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+ /* internal and external reset, stop after that */
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+ __raw_writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0,
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+ WDTIM_MCTRL(wdt_base));
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+ /* configure match output */
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+ __raw_writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
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+ /* clear interrupt, just in case */
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+ __raw_writel(MATCH_INT, WDTIM_INT(wdt_base));
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+ /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */
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+ __raw_writel(0xFFFF, WDTIM_PULSE(wdt_base));
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+ __raw_writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
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+ /*enable counter, stop when debugger active */
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+ __raw_writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));
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+
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+ spin_unlock(&io_lock);
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+}
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+
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+static void wdt_disable(void)
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+{
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+ spin_lock(&io_lock);
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+
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+ __raw_writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */
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+ if (wdt_clk)
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+ clk_set_rate(wdt_clk, 0);
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+
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+ spin_unlock(&io_lock);
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+}
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+
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+static int pnx4008_wdt_open(struct inode *inode, struct file *file)
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+{
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+ if (test_and_set_bit(WDT_IN_USE, &wdt_status))
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+ return -EBUSY;
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+
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+ clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
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+
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+ wdt_enable();
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+
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+ return nonseekable_open(inode, file);
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+}
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+
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+static ssize_t
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+pnx4008_wdt_write(struct file *file, const char *data, size_t len,
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+ loff_t * ppos)
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+{
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+ /* Can't seek (pwrite) on this device */
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+ if (ppos != &file->f_pos)
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+ return -ESPIPE;
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+
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+ if (len) {
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+ if (!nowayout) {
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+ size_t i;
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+
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+ clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
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+
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+ for (i = 0; i != len; i++) {
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+ char c;
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+
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+ if (get_user(c, data + i))
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+ return -EFAULT;
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+ if (c == 'V')
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+ set_bit(WDT_OK_TO_CLOSE, &wdt_status);
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+ }
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+ }
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+ wdt_enable();
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+ }
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+
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+ return len;
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+}
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+
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+static struct watchdog_info ident = {
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+ .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE |
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+ WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
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+ .identity = "PNX4008 Watchdog",
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+};
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+
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+static int
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+pnx4008_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
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+ unsigned long arg)
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+{
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+ int ret = -ENOIOCTLCMD;
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+ int time;
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+
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+ switch (cmd) {
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+ case WDIOC_GETSUPPORT:
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+ ret = copy_to_user((struct watchdog_info *)arg, &ident,
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+ sizeof(ident)) ? -EFAULT : 0;
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+ break;
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+
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+ case WDIOC_GETSTATUS:
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+ ret = put_user(0, (int *)arg);
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+ break;
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+
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+ case WDIOC_GETBOOTSTATUS:
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+ ret = put_user(boot_status, (int *)arg);
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+ break;
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+
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+ case WDIOC_SETTIMEOUT:
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+ ret = get_user(time, (int *)arg);
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+ if (ret)
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+ break;
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+
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+ if (time <= 0 || time > MAX_HEARTBEAT) {
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+ ret = -EINVAL;
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+ break;
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+ }
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+
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+ heartbeat = time;
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+ wdt_enable();
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+ /* Fall through */
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+
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+ case WDIOC_GETTIMEOUT:
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+ ret = put_user(heartbeat, (int *)arg);
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+ break;
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+
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+ case WDIOC_KEEPALIVE:
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+ wdt_enable();
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+ ret = 0;
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+ break;
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+ }
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+ return ret;
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+}
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+
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+static int pnx4008_wdt_release(struct inode *inode, struct file *file)
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+{
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+ if (!test_bit(WDT_OK_TO_CLOSE, &wdt_status))
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+ printk(KERN_WARNING "WATCHDOG: Device closed unexpectdly\n");
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+
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+ wdt_disable();
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+ clear_bit(WDT_IN_USE, &wdt_status);
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+ clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
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+
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+ return 0;
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+}
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+
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+static struct file_operations pnx4008_wdt_fops = {
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+ .owner = THIS_MODULE,
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+ .llseek = no_llseek,
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+ .write = pnx4008_wdt_write,
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+ .ioctl = pnx4008_wdt_ioctl,
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+ .open = pnx4008_wdt_open,
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+ .release = pnx4008_wdt_release,
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+};
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+
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+static struct miscdevice pnx4008_wdt_miscdev = {
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+ .minor = WATCHDOG_MINOR,
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+ .name = "watchdog",
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+ .fops = &pnx4008_wdt_fops,
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+};
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+
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+static int pnx4008_wdt_probe(struct platform_device *pdev)
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+{
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+ int ret = 0, size;
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+ struct resource *res;
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+
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+ spin_lock_init(&io_lock);
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+
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+ if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
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+ heartbeat = DEFAULT_HEARTBEAT;
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+
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+ printk(KERN_INFO MODULE_NAME
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+ "PNX4008 Watchdog Timer: heartbeat %d sec\n", heartbeat);
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ if (res == NULL) {
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+ printk(KERN_INFO MODULE_NAME
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+ "failed to get memory region resouce\n");
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+ return -ENOENT;
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+ }
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+
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+ size = res->end - res->start + 1;
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+ wdt_mem = request_mem_region(res->start, size, pdev->name);
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+
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+ if (wdt_mem == NULL) {
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+ printk(KERN_INFO MODULE_NAME "failed to get memory region\n");
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+ return -ENOENT;
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+ }
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+ wdt_base = (void __iomem *)IO_ADDRESS(res->start);
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+
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+ wdt_clk = clk_get(&pdev->dev, "wdt_ck");
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+ if (!wdt_clk) {
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+ release_resource(wdt_mem);
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+ kfree(wdt_mem);
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+ goto out;
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+ } else
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+ clk_set_rate(wdt_clk, 1);
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+
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+ ret = misc_register(&pnx4008_wdt_miscdev);
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+ if (ret < 0) {
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+ printk(KERN_ERR MODULE_NAME "cannot register misc device\n");
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+ release_resource(wdt_mem);
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+ kfree(wdt_mem);
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+ clk_set_rate(wdt_clk, 0);
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+ } else {
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+ boot_status = (__raw_readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
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+ WDIOF_CARDRESET : 0;
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+ wdt_disable(); /*disable for now */
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+ set_bit(WDT_DEVICE_INITED, &wdt_status);
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+ }
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+
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+out:
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+ return ret;
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+}
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+
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+static int pnx4008_wdt_remove(struct platform_device *pdev)
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+{
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+ misc_deregister(&pnx4008_wdt_miscdev);
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+ if (wdt_clk) {
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+ clk_set_rate(wdt_clk, 0);
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+ clk_put(wdt_clk);
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+ wdt_clk = NULL;
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+ }
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+ if (wdt_mem) {
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+ release_resource(wdt_mem);
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+ kfree(wdt_mem);
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+ wdt_mem = NULL;
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+ }
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+ return 0;
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+}
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+
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+static struct platform_driver platform_wdt_driver = {
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+ .driver = {
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+ .name = "watchdog",
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+ },
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+ .probe = pnx4008_wdt_probe,
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+ .remove = pnx4008_wdt_remove,
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+};
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+
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+static int __init pnx4008_wdt_init(void)
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+{
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+ return platform_driver_register(&platform_wdt_driver);
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+}
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+
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+static void __exit pnx4008_wdt_exit(void)
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+{
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+ return platform_driver_unregister(&platform_wdt_driver);
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+}
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+
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+module_init(pnx4008_wdt_init);
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+module_exit(pnx4008_wdt_exit);
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+
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+MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
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+MODULE_DESCRIPTION("PNX4008 Watchdog Driver");
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+
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+module_param(heartbeat, int, 0);
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+MODULE_PARM_DESC(heartbeat,
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+ "Watchdog heartbeat period in seconds from 1 to "
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+ __MODULE_STRING(MAX_HEARTBEAT) ", default "
|
|
|
|
+ __MODULE_STRING(DEFAULT_HEARTBEAT));
|
|
|
|
+
|
|
|
|
+module_param(nowayout, int, 0);
|
|
|
|
+MODULE_PARM_DESC(nowayout,
|
|
|
|
+ "Set to 1 to keep watchdog running after device release");
|
|
|
|
+
|
|
|
|
+MODULE_LICENSE("GPL");
|
|
|
|
+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
|