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+/*
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+ * arch/sh/kernel/cpu/sh4a/clock-sh7724.c
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+ *
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+ * SH7724 clock framework support
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+ *
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+ * Copyright (C) 2009 Magnus Damm
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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+ */
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+#include <linux/init.h>
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+#include <linux/kernel.h>
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+#include <linux/io.h>
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+#include <asm/clock.h>
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+
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+/* SH7724 registers */
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+#define FRQCRA 0xa4150000
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+#define FRQCRB 0xa4150004
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+#define VCLKCR 0xa4150048
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+#define FCLKACR 0xa4150008
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+#define FCLKBCR 0xa415000c
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+#define IRDACLKCR 0xa4150018
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+#define PLLCR 0xa4150024
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+#define MSTPCR0 0xa4150030
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+#define MSTPCR1 0xa4150034
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+#define MSTPCR2 0xa4150038
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+#define SPUCLKCR 0xa415003c
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+#define FLLFRQ 0xa4150050
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+#define LSTATS 0xa4150060
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+
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+/* Fixed 32 KHz root clock for RTC and Power Management purposes */
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+static struct clk r_clk = {
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+ .name = "rclk",
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+ .id = -1,
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+ .rate = 32768,
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+};
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+
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+/*
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+ * Default rate for the root input clock, reset this with clk_set_rate()
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+ * from the platform code.
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+ */
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+struct clk extal_clk = {
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+ .name = "extal",
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+ .id = -1,
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+ .rate = 33333333,
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+};
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+
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+/* The fll multiplies the 32khz r_clk, may be used instead of extal */
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+static unsigned long fll_recalc(struct clk *clk)
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+{
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+ unsigned long mult = 0;
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+ unsigned long div = 1;
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+
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+ if (__raw_readl(PLLCR) & 0x1000)
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+ mult = __raw_readl(FLLFRQ) & 0x3ff;
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+
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+ if (__raw_readl(FLLFRQ) & 0x4000)
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+ div = 2;
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+
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+ return (clk->parent->rate * mult) / div;
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+}
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+
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+static struct clk_ops fll_clk_ops = {
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+ .recalc = fll_recalc,
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+};
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+
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+static struct clk fll_clk = {
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+ .name = "fll_clk",
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+ .id = -1,
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+ .ops = &fll_clk_ops,
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+ .parent = &r_clk,
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+ .flags = CLK_ENABLE_ON_INIT,
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+};
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+
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+static unsigned long pll_recalc(struct clk *clk)
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+{
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+ unsigned long mult = 1;
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+
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+ if (__raw_readl(PLLCR) & 0x4000)
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+ mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2;
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+
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+ return clk->parent->rate * mult;
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+}
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+
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+static struct clk_ops pll_clk_ops = {
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+ .recalc = pll_recalc,
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+};
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+
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+static struct clk pll_clk = {
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+ .name = "pll_clk",
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+ .id = -1,
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+ .ops = &pll_clk_ops,
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+ .flags = CLK_ENABLE_ON_INIT,
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+};
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+
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+/* A fixed divide-by-3 block use by the div6 clocks */
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+static unsigned long div3_recalc(struct clk *clk)
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+{
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+ return clk->parent->rate / 3;
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+}
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+
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+static struct clk_ops div3_clk_ops = {
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+ .recalc = div3_recalc,
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+};
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+
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+static struct clk div3_clk = {
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+ .name = "div3_clk",
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+ .id = -1,
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+ .ops = &div3_clk_ops,
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+ .parent = &pll_clk,
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+};
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+
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+struct clk *main_clks[] = {
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+ &r_clk,
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+ &extal_clk,
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+ &fll_clk,
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+ &pll_clk,
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+ &div3_clk,
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+};
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+
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+static int divisors[] = { 2, 0, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
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+
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+static struct clk_div_mult_table div4_table = {
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+ .divisors = divisors,
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+ .nr_divisors = ARRAY_SIZE(divisors),
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+};
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+
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+enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
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+
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+#define DIV4(_str, _reg, _bit, _mask, _flags) \
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+ SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
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+
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+struct clk div4_clks[DIV4_NR] = {
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+ [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
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+ [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
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+ [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
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+ [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
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+ [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, 0),
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+};
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+
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+struct clk div6_clks[] = {
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+ SH_CLK_DIV6("video_clk", &div3_clk, VCLKCR, 0),
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+ SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0),
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+ SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0),
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+ SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0),
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+ SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, 0),
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+};
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+
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+#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \
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+ SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT)
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+
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+static struct clk mstp_clks[] = {
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+ MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0),
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+ MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0),
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+ MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0),
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+ MSTP("rs0", &div4_clks[DIV4_B], MSTPCR0, 28, 1, 1, 0),
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+ MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0),
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+ MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 26, 1, 1, 0),
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+ MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0),
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+ MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 1, 1, 0),
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+ MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1),
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+ MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0),
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+ MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0),
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+ MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0),
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+ MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0),
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+ MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0),
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+ MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0),
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+ MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1),
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+ MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0),
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+ MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0),
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+ MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0),
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+ MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0),
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+ MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0),
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+ MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0),
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+ MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0),
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+ MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0),
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+ MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0),
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+
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+ MSTP("keysc0", &r_clk, MSTPCR1, 12, 0, 0, 0),
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+ MSTP("rtc0", &r_clk, MSTPCR1, 11, 0, 0, 0),
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+ MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0),
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+ MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0, 1, 0),
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+
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+ MSTP("mmc0", &div4_clks[DIV4_B], MSTPCR2, 29, 0, 1, 0),
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+ MSTP("eth0", &div4_clks[DIV4_B], MSTPCR2, 28, 0, 1, 0),
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+ MSTP("atapi0", &div4_clks[DIV4_B], MSTPCR2, 26, 0, 1, 0),
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+ MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0),
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+ MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0),
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+ MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0),
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+ MSTP("usb1", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1),
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+ MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 20, 0, 1, 1),
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+ MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 19, 0, 1, 1),
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+ MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0),
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+ MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0),
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+ MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 15, 1, 1, 1),
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+ MSTP("ceu1", &div4_clks[DIV4_B], MSTPCR2, 13, 0, 1, 1),
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+ MSTP("beu1", &div4_clks[DIV4_B], MSTPCR2, 12, 0, 1, 1),
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+ MSTP("2ddmac0", &div4_clks[DIV4_SH], MSTPCR2, 10, 0, 1, 1),
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+ MSTP("spu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0, 1, 0),
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+ MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1),
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+ MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1),
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+ MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1),
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+ MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1),
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+ MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1),
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+ MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1),
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+ MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1),
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+};
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+
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+int __init arch_clk_init(void)
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+{
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+ int k, ret = 0;
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+
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+ /* autodetect extal or fll configuration */
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+ if (__raw_readl(PLLCR) & 0x1000)
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+ pll_clk.parent = &fll_clk;
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+ else
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+ pll_clk.parent = &extal_clk;
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+
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+ for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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+ ret = clk_register(main_clks[k]);
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+
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+ if (!ret)
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+ ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
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+
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+ if (!ret)
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+ ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
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+
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+ if (!ret)
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+ ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
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+
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+ return ret;
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+}
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Magnus Damm