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@@ -62,30 +62,65 @@ int cx23885_vbi_fmt(struct file *file, void *priv,
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return 0;
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}
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+/* We're given the Video Interrupt status register.
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+ * The cx23885_video_irq() func has already validated
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+ * the potential error bits, we just need to
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+ * deal with vbi payload and return indication if
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+ * we actually processed any payload.
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+ */
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+int cx23885_vbi_irq(struct cx23885_dev *dev, u32 status)
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+{
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+ u32 count;
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+ int handled = 0;
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+
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+ if (status & VID_BC_MSK_VBI_RISCI1) {
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+ dprintk(1, "%s() VID_BC_MSK_VBI_RISCI1\n", __func__);
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+ spin_lock(&dev->slock);
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+ count = cx_read(VID_A_GPCNT);
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+ cx23885_video_wakeup(dev, &dev->vbiq, count);
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+ spin_unlock(&dev->slock);
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+ handled++;
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+ }
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+
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+ if (status & VID_BC_MSK_VBI_RISCI2) {
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+ dprintk(1, "%s() VID_BC_MSK_VBI_RISCI2\n", __func__);
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+ dprintk(2, "stopper vbi\n");
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+ spin_lock(&dev->slock);
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+ cx23885_restart_vbi_queue(dev, &dev->vbiq);
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+ spin_unlock(&dev->slock);
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+ handled++;
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+ }
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+
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+ return handled;
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+}
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+
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static int cx23885_start_vbi_dma(struct cx23885_dev *dev,
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struct cx23885_dmaqueue *q,
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struct cx23885_buffer *buf)
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{
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+ dprintk(1, "%s()\n", __func__);
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+
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/* setup fifo + format */
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cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02],
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buf->vb.width, buf->risc.dma);
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/* reset counter */
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+ cx_write(VID_A_GPCNT_CTL, 3);
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q->count = 1;
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- /* enable irqs */
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+ /* enable irq */
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cx23885_irq_add_enable(dev, 0x01);
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cx_set(VID_A_INT_MSK, 0x000022);
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/* start dma */
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cx_set(DEV_CNTRL2, (1<<5));
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- cx_set(VID_A_DMA_CTL, 0x00000022);
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+ cx_set(VID_A_DMA_CTL, 0x22); /* FIFO and RISC enable */
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return 0;
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}
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-static int cx23885_restart_vbi_queue(struct cx23885_dev *dev,
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+int cx23885_restart_vbi_queue(struct cx23885_dev *dev,
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struct cx23885_dmaqueue *q)
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{
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struct cx23885_buffer *buf;
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@@ -115,6 +150,7 @@ void cx23885_vbi_timeout(unsigned long data)
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cx23885_sram_channel_dump(dev, &dev->sram_channels[SRAM_CH02]);
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+ /* Stop the VBI engine */
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cx_clear(VID_A_DMA_CTL, 0x22);
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spin_lock_irqsave(&dev->slock, flags);
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