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@@ -465,18 +465,6 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
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ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1);
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}
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-static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
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-{
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- struct ath_common *common = ath9k_hw_common(ah);
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- int32_t listen_time;
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-
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- ath9k_hw_update_cycle_counters(ah);
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- listen_time = ah->listen_time / (common->clockrate * 1000);
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- ah->listen_time = 0;
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-
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- return listen_time;
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-}
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-
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static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
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{
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struct ar5416AniState *aniState;
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@@ -655,7 +643,9 @@ static void ath9k_hw_ani_read_counters(struct ath_hw *ah)
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u32 phyCnt1, phyCnt2;
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int32_t listenTime;
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- listenTime = ath9k_hw_ani_get_listen_time(ah);
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+ ath_hw_cycle_counters_update(common);
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+ listenTime = ath_hw_get_listen_time(common);
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+
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if (listenTime < 0) {
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ah->stats.ast_ani_lneg++;
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ath9k_ani_restart(ah);
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@@ -796,54 +786,6 @@ void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
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}
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EXPORT_SYMBOL(ath9k_hw_disable_mib_counters);
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-void ath9k_hw_update_cycle_counters(struct ath_hw *ah)
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-{
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- struct ath_cycle_counters cc;
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- bool clear;
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-
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- memcpy(&cc, &ah->cc, sizeof(cc));
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-
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- /* freeze counters */
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- REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
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-
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- ah->cc.cycles = REG_READ(ah, AR_CCCNT);
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- if (ah->cc.cycles < cc.cycles) {
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- clear = true;
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- goto skip;
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- }
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-
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- ah->cc.rx_clear = REG_READ(ah, AR_RCCNT);
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- ah->cc.rx_frame = REG_READ(ah, AR_RFCNT);
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- ah->cc.tx_frame = REG_READ(ah, AR_TFCNT);
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-
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- /* prevent wraparound */
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- if (ah->cc.cycles & BIT(31))
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- clear = true;
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-
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-#define CC_DELTA(_field, _reg) ah->cc_delta._field += ah->cc._field - cc._field
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- CC_DELTA(cycles, AR_CCCNT);
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- CC_DELTA(rx_frame, AR_RFCNT);
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- CC_DELTA(rx_clear, AR_RCCNT);
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- CC_DELTA(tx_frame, AR_TFCNT);
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-#undef CC_DELTA
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-
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- ah->listen_time += (ah->cc.cycles - cc.cycles) -
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- ((ah->cc.rx_frame - cc.rx_frame) +
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- (ah->cc.tx_frame - cc.tx_frame));
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-
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-skip:
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- if (clear) {
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- REG_WRITE(ah, AR_CCCNT, 0);
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- REG_WRITE(ah, AR_RFCNT, 0);
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- REG_WRITE(ah, AR_RCCNT, 0);
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- REG_WRITE(ah, AR_TFCNT, 0);
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- memset(&ah->cc, 0, sizeof(ah->cc));
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- }
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-
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- /* unfreeze counters */
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- REG_WRITE(ah, AR_MIBC, 0);
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-}
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-
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/*
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* Process a MIB interrupt. We may potentially be invoked because
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* any of the MIB counters overflow/trigger so don't assume we're
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