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@@ -236,7 +236,6 @@
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#define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C)
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#define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030)
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-
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/* 4965 SCD memory mapped registers */
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#define KDR_SCD_BASE (PRPH_BASE + 0xa02c00)
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@@ -267,4 +266,15 @@
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#define KDR_SCD_QUERY_MIN_FRAME_SIZE (KDR_SCD_BASE + 0x100)
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#define KDR_SCD_QUEUE_STATUS_BITS(x) (KDR_SCD_BASE + 0x104 + (x) * 4)
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+/* SP SCD */
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+#define SHL_SCD_BASE (PRPH_BASE + 0xa02c00)
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+
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+#define SHL_SCD_AIT (SHL_SCD_BASE + 0x0c)
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+#define SHL_SCD_TXFACT (SHL_SCD_BASE + 0x10)
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+#define SHL_SCD_QUEUE_WRPTR(x) (SHL_SCD_BASE + 0x18 + (x) * 4)
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+#define SHL_SCD_QUEUE_RDPTR(x) (SHL_SCD_BASE + 0x68 + (x) * 4)
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+#define SHL_SCD_QUEUECHAIN_SEL (SHL_SCD_BASE + 0xe8)
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+#define SHL_SCD_AGGR_SEL (SHL_SCD_BASE + 0x248)
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+#define SHL_SCD_INTERRUPT_MASK (SHL_SCD_BASE + 0x108)
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+
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#endif /* __iwl_prph_h__ */
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