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drm/radeon: update cik_gpu_init() for hawaii

This adds the hawaii asic specific configuration
details.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher 12 years ago
parent
commit
b496038bd4
2 changed files with 18 additions and 0 deletions
  1. 17 0
      drivers/gpu/drm/radeon/cik.c
  2. 1 0
      drivers/gpu/drm/radeon/cikd.h

+ 17 - 0
drivers/gpu/drm/radeon/cik.c

@@ -2714,6 +2714,23 @@ static void cik_gpu_init(struct radeon_device *rdev)
 		rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
 		gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
 		break;
+	case CHIP_HAWAII:
+		rdev->config.cik.max_shader_engines = 4;
+		rdev->config.cik.max_tile_pipes = 16;
+		rdev->config.cik.max_cu_per_sh = 11;
+		rdev->config.cik.max_sh_per_se = 1;
+		rdev->config.cik.max_backends_per_se = 4;
+		rdev->config.cik.max_texture_channel_caches = 16;
+		rdev->config.cik.max_gprs = 256;
+		rdev->config.cik.max_gs_threads = 32;
+		rdev->config.cik.max_hw_contexts = 8;
+
+		rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
+		rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
+		rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
+		rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
+		gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
+		break;
 	case CHIP_KAVERI:
 		rdev->config.cik.max_shader_engines = 1;
 		rdev->config.cik.max_tile_pipes = 4;

+ 1 - 0
drivers/gpu/drm/radeon/cikd.h

@@ -25,6 +25,7 @@
 #define CIK_H
 
 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN        0x12010001
+#define HAWAII_GB_ADDR_CONFIG_GOLDEN         0x12011003
 
 #define CIK_RB_BITMAP_WIDTH_PER_SH  2