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@@ -465,7 +465,8 @@
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#define COMEDI_CB_EOS 1 /* end of scan */
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#define COMEDI_CB_EOA 2 /* end of acquisition */
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-#define COMEDI_CB_BLOCK 4 /* data has arrived: wakes up read() / write() */
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+#define COMEDI_CB_BLOCK 4 /* data has arrived:
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+ * wakes up read() / write() */
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#define COMEDI_CB_EOBUF 8 /* DEPRECATED: end of buffer */
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#define COMEDI_CB_ERROR 16 /* card error during acquisition */
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#define COMEDI_CB_OVERFLOW 32 /* buffer overflow/underflow */
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@@ -499,8 +500,10 @@
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I8254_MODE2 = (2 << 1), /* Rate generator */
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I8254_MODE3 = (3 << 1), /* Square wave mode */
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I8254_MODE4 = (4 << 1), /* Software triggered strobe */
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- I8254_MODE5 = (5 << 1), /* Hardware triggered strobe (retriggerable) */
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- I8254_BCD = 1, /* use binary-coded decimal instead of binary (pretty useless) */
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+ I8254_MODE5 = (5 << 1), /* Hardware triggered strobe
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+ * (retriggerable) */
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+ I8254_BCD = 1, /* use binary-coded decimal instead of binary
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+ * (pretty useless) */
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I8254_BINARY = 0
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};
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@@ -640,7 +643,8 @@ May be bitwise-or'd with CR_EDGE or CR_INVERT. */
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NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201,
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NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e,
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/* m-series "second gate" sources are unknown,
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- we should add them here with an offset of 0x300 when known. */
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+ * we should add them here with an offset of 0x300 when
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+ * known. */
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NI_GPCT_DISABLED_GATE_SELECT = 0x8000,
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};
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static inline unsigned NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n)
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@@ -681,14 +685,14 @@ INSN_CONFIG_SET_OTHER_SRC when using NI general-purpose counters. */
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INSN_CONFIG_ARM */
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enum ni_gpct_arm_source {
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NI_GPCT_ARM_IMMEDIATE = 0x0,
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- NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1, /* Start both the counter and
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- the adjacent paired counter
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- simultaneously */
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- /* NI doesn't document bits for selecting hardware arm triggers. If
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- * the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least
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- * significant bits (3 bits for 660x or 5 bits for m-series) through to
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- * the hardware. This will at least allow someone to figure out what
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- * the bits do later. */
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+ NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1, /* Start both the counter
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+ * and the adjacent paired
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+ * counter simultaneously */
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+ /* NI doesn't document bits for selecting hardware arm triggers.
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+ * If the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least
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+ * significant bits (3 bits for 660x or 5 bits for m-series)
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+ * through to the hardware. This will at least allow someone to
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+ * figure out what the bits do later. */
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NI_GPCT_ARM_UNKNOWN = 0x1000,
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};
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@@ -740,8 +744,8 @@ INSN_CONFIG_ARM */
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NI_RTSI_OUTPUT_G_GATE0 = 6,
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NI_RTSI_OUTPUT_RGOUT0 = 7,
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NI_RTSI_OUTPUT_RTSI_BRD_0 = 8,
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- NI_RTSI_OUTPUT_RTSI_OSC = 12 /* pre-m-series always have RTSI clock
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- on line 7 */
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+ NI_RTSI_OUTPUT_RTSI_OSC = 12 /* pre-m-series always have RTSI
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+ * clock on line 7 */
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};
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static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n)
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{
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