|
@@ -33,24 +33,19 @@
|
|
|
cpus {
|
|
|
cpu@0 {
|
|
|
compatible = "arm,cortex-a15";
|
|
|
- timer {
|
|
|
- compatible = "arm,armv7-timer";
|
|
|
- /* 14th PPI IRQ, active low level-sensitive */
|
|
|
- interrupts = <1 14 0x308>;
|
|
|
- clock-frequency = <6144000>;
|
|
|
- };
|
|
|
};
|
|
|
cpu@1 {
|
|
|
compatible = "arm,cortex-a15";
|
|
|
- timer {
|
|
|
- compatible = "arm,armv7-timer";
|
|
|
- /* 14th PPI IRQ, active low level-sensitive */
|
|
|
- interrupts = <1 14 0x308>;
|
|
|
- clock-frequency = <6144000>;
|
|
|
- };
|
|
|
};
|
|
|
};
|
|
|
|
|
|
+ timer {
|
|
|
+ compatible = "arm,armv7-timer";
|
|
|
+ /* 14th PPI IRQ, active low level-sensitive */
|
|
|
+ interrupts = <1 14 0x308>;
|
|
|
+ clock-frequency = <6144000>;
|
|
|
+ };
|
|
|
+
|
|
|
/*
|
|
|
* The soc node represents the soc top level view. It is uses for IPs
|
|
|
* that are not memory mapped in the MPU view or for the MPU itself.
|