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@@ -4090,11 +4090,15 @@ _base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
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writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
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&ioc->chip->HostDiagnostic);
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- /* don't access any registers for 50 milliseconds */
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- msleep(50);
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+ /*This delay allows the chip PCIe hardware time to finish reset tasks*/
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+ if (sleep_flag == CAN_SLEEP)
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+ msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
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+ else
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+ mdelay(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
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- /* 300 second max wait */
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- for (count = 0; count < 3000000 ; count++) {
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+ /* Approximately 300 second max wait */
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+ for (count = 0; count < (300000000 /
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+ MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
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host_diagnostic = readl(&ioc->chip->HostDiagnostic);
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@@ -4103,11 +4107,13 @@ _base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
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if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
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break;
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- /* wait 1 msec */
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+ /* Wait to pass the second read delay window */
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if (sleep_flag == CAN_SLEEP)
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- usleep_range(1000, 1500);
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+ msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
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+ / 1000);
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else
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- mdelay(1);
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+ mdelay(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
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+ / 1000);
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}
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if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
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