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@@ -126,7 +126,7 @@ nv84_therm_intr(struct nouveau_subdev *subdev)
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spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags);
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- intr = nv_rd32(therm, 0x20100);
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+ intr = nv_rd32(therm, 0x20100) & 0x3ff;
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/* THRS_4: downclock */
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if (intr & 0x002) {
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@@ -209,6 +209,19 @@ nv84_therm_ctor(struct nouveau_object *parent,
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return nouveau_therm_preinit(&priv->base.base);
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}
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+int
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+nv84_therm_fini(struct nouveau_object *object, bool suspend)
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+{
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+ /* Disable PTherm IRQs */
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+ nv_wr32(object, 0x20000, 0x00000000);
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+
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+ /* ACK all PTherm IRQs */
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+ nv_wr32(object, 0x20100, 0xffffffff);
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+ nv_wr32(object, 0x1100, 0x10000); /* PBUS */
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+
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+ return _nouveau_therm_fini(object, suspend);
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+}
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+
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struct nouveau_oclass
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nv84_therm_oclass = {
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.handle = NV_SUBDEV(THERM, 0x84),
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@@ -216,6 +229,6 @@ nv84_therm_oclass = {
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.ctor = nv84_therm_ctor,
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.dtor = _nouveau_therm_dtor,
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.init = _nouveau_therm_init,
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- .fini = _nouveau_therm_fini,
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+ .fini = nv84_therm_fini,
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},
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};
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